Digital Electronics – Electrical Engineering Optional PYQs (1995–2026)

Here are all 106 Digital Electronics questions asked in UPSC Electrical Engineering Optional Paper I from 1995 to 2026, arranged under the 7 topics of the official syllabus. Within each topic the latest questions come first.

Each question ends with a code such as [2024/15m/3b] – the year, the marks, the word limit (where UPSC set one) and the question number in the paper.

5.1] Boolean algebra and logic gates

23 questions

1. Consider the control circuitry of a machine copier with four switches as shown below in the figure. These switches are at various points along the path of the machine. Each switch is normally open and closes only when the paper passes over it. Let there be a restriction that switch 1 and switch 4 cannot close simultaneously. Use Karnaugh map to design a logic circuit that produces a high output whenever two or more switches are closed at the same time.

[Figure: Four switches SW1, SW2, SW3, SW4, each connected between a common grounded line and one input line of a block “Logic Circuit”; each input line is pulled up to 5 V through a resistor. The Logic Circuit has output X. Caption: (SW1, SW2, SW3, SW4: Switch 1, Switch 2, Switch 3, Switch 4)] [2023/20m/4b]

2. Consider the four variables logic function defined as follows: $F(A,B,C,D)=\overline{A}C+\overline{A}D+\overline{B}C+\overline{B}D+AB\overline{C}\overline{D}$ Assuming input variables as A, B, C and D, propose a logic circuit using only three logic gates to implement the function. [2021/10m/1e]

3. Design a combinational circuit to implement the minimal sum-of-products of the logic function $F={\Sigma }_{WXYZ}(1,2,3,5,7,11,13)$. [2020/10m/2c]

4. Simplify the following expression using Boolean algebra: $Y=AC+A(B+C)+C(B+C)$ and draw the logic diagram for reduced expression. [2019/10m/5b]

5. Reduce the combinational logic circuit shown in Figure 7(d) to a minimum form.

[Figure: Figure 7(d): Inputs A, B and C each pass through an inverter; the three inverted signals feed a 3-input AND gate; the AND output passes through an inverter to a node; from the node, one path goes to a second AND gate (drawn with only this one input connected) whose output goes to an OR gate; a second path from the node goes directly to another input of the same OR gate; input D goes directly to the third input of the OR gate; the OR gate output is X] [2019/10m/7d]

6. Convert the following logic equation to NAND logic and draw the circuit using NAND gates: $Z=\left(\overline{A+B}\right)C+A\left(\overline{B+C}\right)$ [2018/20m/2a]

7. For the Boolean function $F(W,X,Y,Z)=\Sigma (0,2,5,6,7,8,10,13)$ (i) find all the prime implicants; (ii) give minimal representation; (iii) find minimal two-level realization using NAND gates only. [2017/20m/2a]

8. Prove that $\overline{A}B+\overline{B}C+\overline{A}C=\overline{A}B+\overline{B}C$. [2017/10m/5a]

9. Minimize the SOP terms given for a Boolean function $f(A,B,C,D)=\Sigma m(2,3,8,10,11,12,14,15)$ Implement the minimized function using NAND gates alone. [2016/10m/5a]

10. Obtain all the possible minimal functions for: $F=\Sigma (0,2,3,4,5,7)$. [2015/10m/5e]

11. (i) Find 2’s complement of the following numbers: (1) 10010010 (2) 11011000 (ii) Convert the logical equation $Y=(A+BC)(B+\overline{C}A)$ into product-of-sums (POS) form and design circuits using (1) OR and AND gates and (2) NOR gates. (iii) Explain the function of Schottky diode connected between the collector and base of transistors of TTL gate. [2014/20m/6b]

12. Determine the MSP form of the switching function $F\left(uvwxyz\right)=\Sigma (0,1,4\mathrm{\text{–}}6,11,14\mathrm{\text{–}}17,20\mathrm{\text{–}}22,30,32,33,36,37,48,49,52,53,59,63)$ using 6-variable Karnaugh map. [2013/20m/6a]

13. Assuming that logic 0 is available, show that the INCLUSION gate is a universal building block. [2013/10m/6c]

14. Convert decimal 65,535 to its hexadecimal and binary. [2012/12m/5b]

15. Convert decimal number 40 into binary and hexadecimal numbers. [2011/20m/6a]

16. Design a combinational logic circuit which produces an output equal to ‘1’ if the input variables have more 1’s in the sequence than 0’s. The output is zero otherwise. Design the circuit for three variable inputs. Draw the realization. [2009/10m/7a(i)]

17. Implement an OR gate with AND and NOT gates. [2007/5m/5b(ii)]

18. Minimize and implement the following multiple-output functions $f_1(A,B,C,D)=\Sigma (1,2,3,6,8,12,14,15)$ $f_2(A,B,C,D)=\Sigma (1,2,3,5,6,7,8,12,13)$ [2006/10m/6a(iii)]

19. A locker can be opened by A and B when they are both there, as the locker has 2 keys, one of which is with A and the other with B. C has both the keys, but he is permitted to open the locker only when B is not there. Show that the locker can be opened always if both A and C are there. Give the Boolean identity that symbolisms this situation. [2002/20m/3a]

20. A farmer (F) has two sheds ($N_1$ & $S_1$) in his farm to keep his farm produce and belongings. He keeps vegetables (V) as farm produce, a goat (G) which can eat the vegetables and a dog (D) that can bite the goat in the absence of the farmer. The farmer along has to manage both sheds without loosing either vegetables or the goat. Suggest a logic circuit that can alarm him under any catastrophic condition by means of a buzzer. [2001/20m/1b]

21. Simplify the Boolean function $Z=\overline{(A+\overline{B})}.B.(A+\overline{C})$ and realise it using NAND gates. [1999/10m/5b(i)]

22. Reduce the following four variable function using Karnaugh map and implement it in NAND logic, $F=\Sigma m(0,4,12,8,13,7,15)$ [1998/20m/2c]

23. Minimize the following logic functions using Karnaugh maps and realize them using NAND gates. (i) $f(A,B,C,D)=\Sigma m(2,3,6,7,8,9,10,11,12,13,14,15,)$ (ii) $f(A,B,C,D)=\Pi M(0,1,2,3,4,5,6,7,8,9,10,12,13)$ [1997/20m/5a]

5.2] Digital IC families

10 questions

1. Draw the circuit diagram, function table, logic symbol and switch model for a CMOS gate (using six transistors) with two inputs $A$ and $B$ and an output $Z$, such that $Z=0\mathrm{\text{if}}A=1\mathrm{\text{and}}B=0,\mathrm{\text{and}}Z=1\mathrm{\text{otherwise}}$ [2024/20m/2a]

2. (i) Find 2’s complement of the following numbers: (1) 10010010 (2) 11011000 (ii) Convert the logical equation $Y=(A+BC)(B+\overline{C}A)$ into product-of-sums (POS) form and design circuits using (1) OR and AND gates and (2) NOR gates. (iii) Explain the function of Schottky diode connected between the collector and base of transistors of TTL gate. [2014/20m/6b]

3. Specify power supply voltage range, output logic 1 level voltage and output logic 0 level voltage for standard TTL gates. [2013/10m/5a]

4. Draw the circuit of TTL NAND gate and explain its operation. [2010/5m/1b(ii)]

5. The above circuit is intended for NOT operation for input levels 0 and 10 V. Calculate the minimum value of R for which this operation is possible. Assume $h_{FE}=30$, $V_{BE\left(sat\right)}=0.8$, $V_{CE\left(sat\right)}=0.2$ in respect of above silicon transistor.

[Figure (printed before the text): NPN transistor inverter: input $V_i$ through a 10 kΩ resistor (current $i_1$) to the base node; from the base node a resistor R (current $i_2$ flowing down) to a −10 V supply; base current $I_B$ into the base; collector connected through a 2 kΩ resistor (current $I_C$ flowing down) to $V_{CC}=10$ V; output $V_o$ taken at the collector; emitter grounded] [2007/10m/5b(i)]

6. Draw a positive logic OR gate with two diodes and explain its operation. [2007/5m/5b(iii)]

7. Describe what happens to each of the following CMOS characteristics as $V_{DD}$ is increased (i) Noise margin (ii) Power dissipation (iii) Switching speed. [2006/5m/4a(iv)]

8. Draw the circuit diagram of a NOR gate using MOS transistors (n-channel) and verify the NOR operation with. The description of the functioning of this gate. [1997/15m/6a]

9. Show that the NMOS circuit of Fig. 5b is a NAND gate for positive logic. Write down the various combinations of inputs and output in a tabular form and clearly state the meanings of any symbols or parameters used therein.

[Figure: Fig. 5b: Two n-channel MOSFETs $Q_2$ (upper, gate input $v_2$) and $Q_1$ (lower, gate input $v_1$) in series between the output node and ground; load MOSFET $Q_3$ (drawn horizontally, gate lead drawn upwards) between the output node and $+V_{DD}$; output $v_o$ taken from the node joining $Q_3$ and the drain of $Q_2$] [1996/20m/5b]

10. Explain what you understand by: (i) MMIC (ii) MOSFET (iii) NMOS Growth (iv) CMOS Development (v) RAM Device (vi) SRAM Cell (vii) DRAM Cell. [1996/20m/12c]

5.3] Combinational circuits

22 questions

1. A combinational logic circuit consisting of two numbers of 2 to 4 decoders is shown in the figure below: In this circuit, $(A_1,B_1)$ are the inputs and $(D_0$ to $D_3)$ are the outputs of the first decoder, while $(A_2,B_2)$ are the inputs and $(Y_0$ to $Y_3)$ are the outputs of the second decoder. Determine the logic expressions for $Y_1$ and $Y_2$ in terms of $X$ and $Y$.

[Figure: First “2 to 4 Decoder”: input $X$ → $A_1$, input $Y$ → $B_1$; outputs $D_0$, $D_1$, $D_2$, $D_3$ ($D_1$ and $D_2$ are left unconnected, ending in dots). $D_0$ and $D_3$ are each connected to both gates: an XOR gate with inputs $D_0$ (upper) and $D_3$ (lower), whose output drives $A_2$; and an XNOR gate (XOR with output bubble) with inputs $D_0$ (upper) and $D_3$ (lower), whose output drives $B_2$. Second “2 to 4 Decoder”: inputs $A_2$, $B_2$; outputs $Y_0$, $Y_1$, $Y_2$, $Y_3$] [2026/10m/1d]

2. Consider the Boolean function: $F(A,B,C,D)=\sum m(1,3,4,11,12,13,14,15)$ Implement it with a 4-to-1 multiplexer and external gates. Connect inputs A and B to the selection lines. Input to the four data lines is a function of the variables C and D which are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01, 10 and 11. Functions are to be implemented with external gates. [2025/20m/3a]

3. A Binary Coded Decimal (BCD) code is to be transmitted to a remote receiver. Bits are arranged as $A_3{A}_2{A}_1{A}_0$. Design a circuit at the receiving end which has an error detector to check the legal BCD code and produce a HIGH for any error condition. [2024/10m/1d]

4. Find the logic equations for the outputs in the concise form and write the corresponding truth table for the circuit given below:

[Figure: Logic circuit with inputs $D_0$ and $D_1$ and four NAND gates. Gate G1: 2-input NAND with inputs $D_0$ and $D_1$; its output line N runs vertically. Gate G2: 2-input NAND with inputs $D_0$ and N; output $\overline{Y_1}$. Gate G3: 2-input NAND with inputs N and $D_1$; output $\overline{Y_2}$. Gate G4: 3-input NAND with inputs N, $\overline{Y_1}$ and $\overline{Y_2}$; output $\overline{Y_0}$. Line N is also taken out directly as output $\overline{Y_3}$.] [2024/10m/3c]

5. A circuit using three 2-input multiplexers is shown below. Determine the function performed by this circuit:

[Figure: Inside a dashed box: upper MUX with data inputs $I_3$ (top) and $I_2$, output $Z_2$; lower MUX with data inputs $I_1$ (top) and $I_0$, output $Z_1$; the select inputs S of both these MUXes are connected together to external input $S_1$. A third MUX takes $Z_2$ (upper input) and $Z_1$ (lower input), its select S driven by external input $S_0$; its output is $Z$.] [2024/10m/4c]

6. Use $4:1$ multiplexer and logic gates to implement the function: $F(A,B,C,D)=\Sigma m(3,4,5,6,7,9,10,12,14,15)$ [2023/10m/3a(ii)]

7. Explain the parity bit generator and parity bit checker. Realize the even parity bit generator and even parity bit checker using X-OR gate. [2022/10m/1e]

8. Draw the diagram of cascading BCD adders to add two three-digit decimal numbers. Also explain the function of this adder with suitable example. [2022/10m/8a(ii)]

9. (i) Verify by determining the logic equation for the output and by constructing the truth table for the logic circuit shown in Figure 4(b). (ii) Use an 8 to 1 multiplexer and logic gates to implement the following function: $F(A,B,C,D,E)=\sum m(0,1,2,4,5,6,7,13,14,20,21,\dots ,28,29,30,31)$

[Figure: Figure 4(b): Four 2-to-1 multiplexers with data inputs $D_0$ (0) / $D_1$ (1), $D_2$ (0) / $D_3$ (1), $D_4$ (0) / $D_5$ (1) and $D_6$ (0) / $D_7$ (1); their select inputs are all connected to a common line $S_0$. Their outputs feed a 4-to-1 multiplexer: the $D_0/D_1$ multiplexer to input 00, $D_2/D_3$ to 01, $D_4/D_5$ to 10 and $D_6/D_7$ to 11. The 4-to-1 multiplexer has select inputs $S_2$, $S_1$ and output Y.] [2021/20m/4b]

10. Draw a block diagram to implement logic $F=A\cdot B$ using a $4\times 1$ multiplexer. [2013/10m/5e]

11. Implement the following: (i) Half-adder using basic gates (ii) $T$ flip-flop using $J$–$K$ flip-flop (iii) 2 to 4 decoder using 1×4 demultiplexers. [2011/15m/5a]

12. Design a binary to Gray code converter. [2010/10m/3a(ii)]

13. Realize a half-adder circuit using only NOR gates. [2009/15m/5b]

14. Design a 2-input, 3-output circuit which can be used as half adder or half subtractor by choosing output points. [2006/5m/1b(iv)]

15. Design a combinational circuit that accepts a three-bit number and generates an output binary number equal to the square of the input number. [2005/10m/1b(i)]

16. Implement the Boolean function $F(A,B,C,D)\Sigma (0,1,3,4,8,9,15)$ with an $8\times 1$ multiplexer with A, B and D connected to selection lines $s_2$, $s_1$, $s_0$, respectively. [2005/5m/3a(iii)]

17. Using multiplexers, implement a full adder circuit. [2003/10m/8a(i)]

18. Devise a 4-bit odd parity generator function using 3-level NOT-NOR-NOR logic. [2002/20m/7a]

19. .

(i) Draw the truth table of an octal-to-binary encoder with the condition that the output F = 1 when at least one of the inputs is a 1. The octal input with highest number has the highest priority. What is the condition of binary outputs and F output, if the inputs $D_5=D_3=1$? [2001/10m/3a(i)]

(ii) Design a combinational circuit using AND gates and half adders that can multiply two 2-bit numbers $a_1{a}_0$ and $b_1{b}_0$ to produce 4-bit number $S_3$, $S_2$, $S_1$ and $S_0$. [2001/10m/3a(ii)]

20. .

(i) Design a combinational circuit having 3 inputs and 6 outputs with the condition that the output number is square of the input number. [2000/10m/5b(i)]

(ii) A computer uses RAM chips of capacity 1024 × 1. How many chips are required and how their address and data bus be connected to provide a memory capacity of 1024 bytes? How chips would be connected to provide memory of 16 K bytes? [2000/10m/5b(ii)]

21. It is desired to add two one-bit binary words and produce the result as Sum and Carry. Prepare a truth table, Karnaugh map and Boolean expressions to design a Half-Adder using minimum number of NAND gates. [1997/20m/5b]

22. Design a combinational logic circuit to generate the 2’s complement of a 2-bit number. You may use two full adders and other gates as required but keeping the number of other gates to a minimum. [1996/20m/8c]

5.4] Sequential circuits

27 questions

1. Design a MOD-6 synchronous DOWN counter using $J$–$K$ flip-flops. [2026/20m/6a]

2. Design a sequential circuit with two D flip flops A and B and one input X. Let the state of the circuit remain the same for X = 0. However, when X = 1, the circuit goes through the state transitions from 00 to 10 to 11 to 01, back to 00 and then repeats. [2025/10m/1d]

3. Consider the shift register shown in the figure below, which is implemented using D flip-flops and $2:1$ multiplexers.

[Figure: Four D flip-flops 0, 1, 2, 3 (outputs $Q_0$, $Q_1$, $Q_2$, $Q_3$), each fed at its D input by a 2:1 multiplexer. MUX 0: input 0 = $X_L$, input 1 = $X_0$. MUX 1: input 0 = $Q_0$, input 1 = $X_1$. MUX 2: input 0 = $Q_1$, input 1 = $X_2$. MUX 3: input 0 = $Q_2$, input 1 = $X_3$. The select inputs of all four multiplexers are connected to the common Load line. The clock inputs of all flip-flops are connected to CK and their CLR inputs to the common $\overline{CLR}$ line. Output $Q_3$ taken from flip-flop 3.]

Complete the truth table shown as follows:

CK (Inputs)	$\overline{CLR}$ (Inputs)	Load (Inputs)	$Q_3$ (Next State)	$Q_2$ (Next State)	$Q_1$ (Next State)	$Q_0$ (Next State)
X	0	X
↑ (rising edge)	1	0
↑ (rising edge)	1	1

Complete the timing diagram below assuming $X_3{X}_2{X}_1{X}_0=0101$.

[Figure: Timing diagram: CK with 13 clock pulses, dotted vertical lines at the rising edges of pulses 2 to 12. $\overline{CLR}$ high throughout, going low just after the 12th rising edge (low during the last pulse). Load: low, goes high during the first clock pulse and returns low after the 2nd rising edge (high only at the 2nd rising edge), then stays low. $X_L$: low, high from between the 7th and 8th rising edges to between the 9th and 10th rising edges (high at the 8th and 9th rising edges), then low. Rows $Q_0$, $Q_1$, $Q_2$, $Q_3$ left blank to be completed.] [2023/10m/3a(i)]

4. The diagram of Master-Slave S-R flip-flop and the waveform applied to the Master flip-flop is shown in Figure 5(a). Draw the waveform that appears at the output of Slave flip-flop.

[Figure: Figure 5(a), Master-Slave S-R flip-flop built from NAND gates: input S and clock C go to NAND gate $G_1$; C and input R go to NAND gate $G_2$. The outputs of $G_1$ and $G_2$ drive a cross-coupled NAND latch $G_3$ (output $Q_1$) and $G_4$ (output $\overline{Q_1}$), each latch gate also taking the other’s output. C is also taken (by a wire running along the bottom) to an inverter whose output is $\overline{C}$. $Q_1$ and $\overline{C}$ go to NAND gate $G_5$; $\overline{Q_1}$ and $\overline{C}$ go to NAND gate $G_6$. The outputs of $G_5$ and $G_6$ drive a cross-coupled NAND latch $G_7$ (output $Q_2$) and $G_8$ (output $\overline{Q_2}$). Input waveform (versus t): CLK is a train of four positive pulses numbered 1, 2, 3, 4; dashed vertical lines mark the falling edges of pulses 1, 2 and 3. S is low until the falling edge of pulse 1, high from the falling edge of pulse 1 to the falling edge of pulse 2, and low thereafter. R is high until the falling edge of pulse 1, low from the falling edge of pulse 1 to the falling edge of pulse 2, high from the falling edge of pulse 2 to the falling edge of pulse 3, and low thereafter.] [2022/10m/5a]

5. Differentiate between the functions of Decade counter and BCD counter with example. [2022/10m/8a(i)]

6. Consider the circuit shown in Figure 2(c) below. Let inputs A, B and C be all initially LOW. Output Y is supposed to go HIGH only when A, B and C go HIGH in a certain sequence. Determine the sequence that will make Y go HIGH. Modify this circuit to use D-Flip-flops.

[Figure: Figure 2(c): Two J-K flip-flops. First flip-flop: J = A, CLK = B, K connected to ground, output X. Second flip-flop: J = X, CLK = C, K connected to ground, output Y. The active-low CLR inputs (bubbles) of both flip-flops are connected together to a Start line, shown as a negative-going (LOW) pulse.] [2021/10m/2c]

7. Design a synchronous sequential circuit with D-flip-flops for a state diagram shown in Figure 4(b).

[Figure: Figure 4(b): State diagram with states 000, 001, 010, 011, 100, 101, 110, 111 and transitions 000 → 001, 001 → 100, 100 → 111, 111 → 101, 101 → 000, 110 → 101, 010 → 000, 011 → 100] [2020/20m/4b]

8. Convert a D flip flop to function as an S-R flip flop. Draw the circuit. [2018/10m/5a]

9. Design a synchronous counter using D flip flop that counts in the following sequence: 6, 3, 5, 0, 2, 6, 3, 5, 0, 2, 6, … Draw the circuit. [2018/20m/7b]

10. Find the state transition diagram and realization using J-K flip-flops to count Mod 7 in the following sequence: 000, 001, 011, 100, 101, 111. [2017/20m/7b]

11. Divide by N counter is shown in the figure below. If initially $Q_0=0$, $Q_1=1$, $Q_2=0$, what is the value of N?

[Figure: Three JK flip-flops FF2, FF1, FF0 (left to right) with a common CLOCK to all $C_K$ inputs. Connections: $J_2={\overline{Q}}_1$, $K_2=Q_0$; $J_1=Q_2$, $K_1={\overline{Q}}_2$; $J_0=Q_1$, $K_0={\overline{Q}}_1$. Outputs $Q_0$ and ${\overline{Q}}_0$ brought out on the right] [2015/20m/6b]

12. Design a circuit that gives the input-output relationship shown in Fig. 4.

[Figure: Fig. 4 – Timing diagram. Input: a train of five positive rectangular pulses numbered 1, 2, 3, 4, 5. Output: low throughout, goes high at the falling (trailing) edge of input pulse 4 and returns low at the falling edge of input pulse 5 (dashed lines mark these two edges); i.e. one output pulse lasting from the end of pulse 4 to the end of pulse 5.] [2014/10m/5e]

13. A sequential machine produces an output of 1 only when exactly two 0’s are followed by a 1 or exactly two 1’s are followed by a 0. Determine the reduced state table of the machine. [2013/20m/6b]

14. Show how a D flip-flop can be converted to SR flip-flop. [2012/12m/5a]

15. Indicate how many flip-flops are required to construct each of the following counters: (i) mod–3 (ii) mod 6 (iii) mod–9. [2012/20m/6a]

16. Implement the following: (i) Half-adder using basic gates (ii) $T$ flip-flop using $J$–$K$ flip-flop (iii) 2 to 4 decoder using 1×4 demultiplexers. [2011/15m/5a]

17. Draw symbolic representation for +ve edge triggered clock input in a flip-flop and mark transition time by an arrow in clock input waveform for it. [2011/20m/6b]

18. Design a decade counter using JK FF’s (MOD-10 counter) and draw the timing diagrams. [2010/8m/2b(iii)]

19. Convert a clocked SR Flip-Flop to a clocked JK FF. [2010/10m/7a(ii)]

20. The figure below shows a divide-by-$N$ counter.

(i) Find $N$. Assume initial value of $Q_0=1$, $Q_1=0$ and $Q_2=0$. [2009/10m/2b(i)]

(ii) Repeat Part (i), if initially $Q_0=1$, $Q_1=0$ and $Q_2=1$.

[Figure: Synchronous counter of three JK flip-flops (FF2, FF1, FF0 from left to right), the common Clock line connected to all three Ck inputs; $Q_2\to J_1$, ${\overline{Q}}_2\to K_1$; $Q_1\to J_0$ (crossing the vertical feedback line without connection); ${\overline{Q}}_1\to K_0$ and also, from a junction dot on the ${\overline{Q}}_1$ line, fed back up and over the top to $J_2$; $Q_0$ fed back along the bottom to $K_2$; ${\overline{Q}}_0$ unconnected] [2009/10m/2b(ii)]

21. The waveforms shown in the figure below are applied to– 1. positive edge-triggered SR flip-flop; 2. master-slave SR flip-flop. Draw the output waveforms in each case.

[Figure: Timing diagram. Clock: five positive pulses; the edges are labelled in order a (rising), b (falling), c (rising), d (falling), e (rising), f (falling), g (rising), h (falling), i (rising), j (falling). S: low at first, goes high shortly before a, goes low between b and c, high between d and e, low between f and g, high between g and h, low between h and i, and stays low to the end. R: low at first, goes high between b and c (at the same instant S goes low), low between c and d, high between f and g (at the same instant S goes low), low between g and h (at the same instant S goes high), high again between i and j and stays high to the end] [2009/10m/7a(ii)]

22. A partially filled truth table of a sequence generator (3-D flip-flops in cascade) is given below. Find the sequence generated. $Q_0$ is LSB and $Q_2$ is MSB.

State	$Q_2$	$Q_1$	$Q_0$
1	1		0
2	0
3
4	1
5	0	1
6
7	1	1
1		0	0

[2007/10m/1b(i)]

23. Draw the logic diagram and timing diagram of a 3-bit binary ripple up counter using positive edge triggered FF’s. [2006/5m/8a(iv)]

24. A sequential circuit has one input and one output. The state diagram is shown in the figure. Design the sequential circuit using D flip-flop.

[Figure: State diagram with five states 000, 001, 010, 011, 100; transitions labelled input/output: 001 → 001 on 0/0 (self-loop), 001 → 100 on 1/1; 100 → 011 on 1/0, 100 → 010 on 0/0; 011 → 001 on 0/0, 011 → 010 on 1/1; 010 → 010 on 0/0 (self-loop), 010 → 000 on 1/1 (printed “1/3”); 000 → 100 on 1/1; a line labelled 0/0 joins 011 and 000 (arrowhead direction unclear in the scan, probably 000 → 011) [?].] [2005/5m/6a(iii)]

25. The clock frequency of 1000 ns is connected to a 3-bit asynchronous counter with each flip-flip having 50 ns propagating delay. Which slate will never occur in it, if the clock frequency is decreased to 100 ns? Explain it by drawing wave- shapes for 1000 ns and 100 ns clock frequencies separately. [2000/20m/2a]

26. What is a race condition? How is it prevented? [1999/10m/5b(ii)]

27. The circuit shown in Fig. Q. 5(d) is using master-slave flip-flops. $V_{CC}$ is high and can be taken to be 1. Find $B_0$ and $B_1$ for the first seven clock cycles after these are initially cleared. Give precise explanations for your answers.

[Figure: Fig. Q.5(d): Two JK master-slave flip-flops. FF1: inputs $J_1$ and $K_1$ tied together to $V_{CC}$; clock input $C_1$ driven by CLK; output $Q_1$ gives $B_0$ and also drives the clock input $C_2$ of FF2. FF2: inputs $J_2$ and $K_2$ tied together to terminal A (note: “A is at $V_{CC}$”); output $Q_2$ gives $B_1$. The clear (CR) inputs of both flip-flops are joined and taken through a switch to $V_{CC}$] [1995/20m/5d]

5.5] Comparators, timers and multivibrators

5 questions

1. Implement Astable Multivibrator using NAND gates and explain its operation. [2019/10m/6c]

2. A comparator and limiter circuit is shown in Fig. 2. Develop transfer characteristics $V_O$ vs. $V_I$ and explain.

[Figure: Fig. 2 – Op-amp inverting circuit: input $V_I$ through resistor $R_1$ to the inverting (–) input; non-inverting (+) input grounded. Feedback from the output $V_O$ to the inverting input through resistor $R_2$, and in parallel with $R_2$ two Zener diodes connected back to back in series (cathode to cathode): Zener $V_{Z_2}$ with its anode at the inverting-input side, and Zener $V_{Z_1}$ with its anode at the output side.] [2014/10m/1d]

3. Using IC 555 and other suitable components, draw the circuit diagram of a missing pulse detector and explain its working. [2011/20m/4b]

4. Realize an Astable Multivibrator using 555 timer to produce a square wave of frequency 1 kHz with duty cycle of 50%. Mention three applications of timer. [2010/7m/5b(iii)]

5. Design an astable multivibrator with LM 555. Calculate also the duty cycle and frequency of oscillation. [1999/10m/2b(ii)]

5.6] Sample and hold circuits, ADCs and DACs

9 questions

1. Draw the block diagram of a single slope type A/D converter and explain its principle of operation. [2019/20m/8a]

2. Identify the circuit shown in Fig. 6(a). Briefly explain the same. Calculate the current $i$ and $V_o$, if $V_R=5V$ and $R=5k\Omega =R_F$:

[Figure: Fig. 6(a): R–2R resistor ladder feeding an op-amp: reference $V_R$ at the left node N0; series resistors $R$ from N0 to N1, $R$ from N1 to N2, $R$ from N2 to N3; from N3 a final $2R$ resistor to ground carrying current $i$ (arrow from N3 towards this 2R). Shunt $2R$ resistors: from N0 to ground; from N1 to the op-amp inverting-input line; from N2 to ground; from N3 to the op-amp inverting-input line. Op-amp: inverting (−) input joined to the lines from the N1 and N3 shunt resistors, feedback resistor $R_F$ from output $V_o$ to the inverting input, non-inverting (+) input grounded] [2016/20m/6a]

3. With the aid of circuit, draw $R/2R$ ladder DAC and discuss its operation. [2010/6m/6b(ii)]

4. With $V_{REF}=5V$ for the DAC, find the resolution and full-scale output of this converter. [2010/4m/6b(iii)]

5. A D/A converter has the lowest and the highest values of resistances 1 kΩ and 4 kΩ, respectively. If the bit-length of the converter is to be increased by 2, what would be the number of resistors required and their values? Draw the complete circuit of the new converter. [2007/10m/1b(ii)]

6. Determine (1) maximum conversion rate (2) average conversion rate (3) maximum conversion time for a 16–bit counter type A/D converter using a 1 MHz clock. [2006/5m/5b(iv)]

7. Describe any two types of A to D converters. Discuss their merits and demerits. [1999/20m/6c]

8. For the R-2R type of digital-to-analog converter shown in Fig. 4c, find the output voltage when $S_4$ is closed and $S_3$, $S_2$ and $S_1$ are grounded.

[Figure: Fig. 4c: R-2R ladder DAC. Reference battery $V_B$ = 15 V [?] (+ at top) between a top reference line and ground. Ladder line along the bottom: from ground a 2R resistor to node P, R from P to Q, R from Q to S, R from S to T. Four 2R legs hang from nodes P, Q, S and T respectively; the upper end of each leg goes to a changeover switch ($S_4$ for P, $S_3$ for Q, $S_2$ for S, $S_1$ for T) that connects it either to the top reference line ($V_B$) or to ground. Node T feeds the non-inverting input of an op-amp connected as a voltage follower (output joined to the inverting input); output $v_o$] [1996/20m/4c]

9. Describe a successive approximation type of an A to D converter and give its merits. Find the conversion time and the resolution of an 8-bit ADC of this type when the clock period is 1.25 μs. [1995/20m/8c]

5.7] Memories and programmable logic

10 questions

1. Design a Programmable Logic Array (PLA) for a combinational logic circuit that computes the square of 3-bit binary numbers. Determine the minimum number of product terms required and construct the corresponding PLA programming table for the implementation. [2026/20m/7a]

2. Implement the following Boolean functions with a 4 × 3 Programmable Logic Array (PLA): $F_1=\overline{B}\overline{C}+A\overline{B}$; $F_2=AB\overline{C}+A\overline{B}C\overline{D}$; $F_3=\overline{A}\overline{B}\overline{C}D+A\overline{B}CD$ [2020/10m/1e]

3. What is a PLA? Realize the following functions using an appropriate PLA: $f_1=AB+CD$ $f_2=\overline{A}B+A\overline{B}$ $f_3=AD+BC+\overline{B}D$ [2016/10m/7a]

4. What would be the binary address for a memory system having a capacity of ${10}^{24}$ bits. For the above memory system, what is the decimal address for the binary address 1011001101? What is the address in hexadecimal? [2012/20m/7a]

5. Write the full form of FPGA and explain why it is useful for prototyping of digital circuits. [2011/20m/6c]

6. Using a bipolar $32\times 8$ PROM, implement the following equations simultaneously: $F_1=\Sigma m(0,1,3,5,7,21)$; $F_2=\Sigma m(2,3,4,7,11,12,15,26)$; $F_3=\Sigma m(8,9,11,13,20,23)$ [2005/5m/7a(iii)]

7. It is desired to generate the following three Boolean functions $F_1=a\overline{b}c+\overline{a}b\overline{c}+bc$; $F_2=a\overline{b}c+ab+\overline{a}b\overline{c}$; $F_3=\overline{a}\overline{b}\overline{c}+abc+\overline{a}c$ By using an OR gate array as shown in Figure, where $P_1$ to $P_5$ are the product terms in one or more of the variables, $a,\overline{a},b,\overline{b},c$ and $\overline{c}$. Write down the terms $P_1$, $P_2$, $P_3$, $P_4$ and $P_5$.

[Figure: OR array with five horizontal product-term lines $P_1$ to $P_5$ (top to bottom) and three vertical output lines $F_1$, $F_2$, $F_3$; connections (dots) at: $F_1$ – $P_1$ and $P_2$; $F_2$ – $P_2$ and $P_3$; $F_3$ – $P_4$ and $P_5$.] [2003/10m/8a(ii)]

8. .

(i) Design a combinational circuit having 3 inputs and 6 outputs with the condition that the output number is square of the input number. [2000/10m/5b(i)]

(ii) A computer uses RAM chips of capacity 1024 × 1. How many chips are required and how their address and data bus be connected to provide a memory capacity of 1024 bytes? How chips would be connected to provide memory of 16 K bytes? [2000/10m/5b(ii)]

9. Name the different types of Read- Only-Memories and briefly discuss their attributes in terms of programmability volatility, erasability, technology used and utility. [1997/20m/6b]

10. Explain what you understand by: (i) MMIC (ii) MOSFET (iii) NMOS Growth (iv) CMOS Development (v) RAM Device (vi) SRAM Cell (vii) DRAM Cell. [1996/20m/12c]

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Last updated: 30 October 2026