Analog Electronics – Electrical Engineering Optional PYQs (1995–2026)

Here are all 141 Analog Electronics questions asked in UPSC Electrical Engineering Optional Paper I from 1995 to 2026, arranged under the 8 topics of the official syllabus. Within each topic the latest questions come first.

Each question ends with a code such as [2024/15m/3b] – the year, the marks, the word limit (where UPSC set one) and the question number in the paper.

4.1] Semiconductor devices and equivalent circuits

21 questions

1. For the following circuit given in Fig. (1) below, the diode has the $I$–$V$ characteristic in forward direction as shown in Fig. (2): Find the (i) diode current, (ii) diode power loss and (iii) power supplied by the source.

[Figure: Fig. (1): bridge (diamond) circuit with top, left, right and bottom nodes: $2.0\Omega$ from top to left node; $6.0\Omega$ from top to right node; $8.0\Omega$ from left node to bottom node; $8.0\Omega$ from right node to bottom node; ideal-symbol diode in the vertical branch from top node (anode) to bottom node (cathode), diode current $i_d$ marked downward; a 20 V battery connected between the left and right nodes (through wires running below the bridge; polarity not marked legibly). Fig. (2): diode forward characteristic $i_d$ versus $v_d$: $i_d=0$ up to $v_d=0.7V$, then rises linearly to $i_d=1.0A$ at $v_d=0.9V$ (dashed lines mark 1.0 A and 0.9 V)] [2026/20m/3b]

2. For the Schottky transistor circuit shown below, determine $I_B$, $I_D$, $I_C$ and $V_{CE}$. Next, remove the Schottky diode and determine $I_B$, $I_D$, $I_C$ and $V_{CE}$ assuming additional values of $V_{BE}\left(\mathrm{\text{sat.}}\right)=0.8V$ and $V_{CE}\left(\mathrm{\text{sat.}}\right)=0.1V$. Assume parameter values of $\beta =50$, $V_{BE}\left(\mathrm{\text{on}}\right)=0.7V$ and $V_f=0.3V$ for the Schottky diode.

[Figure: NPN transistor with emitter to ground. Base circuit: $V_{BB}=5.8V$ (+ at top, − at ground) in series with $R_S=10k\Omega$ to the base node; base current $I_B$ marked into the base. Schottky diode from the base node (anode) to the collector (cathode), diode current $I_D$ marked from base side towards collector. Collector circuit: collector current $I_C$ marked downward into the collector; collector connected through $R_C=1k\Omega$ to $V_{CC}=5V$ (+ at top, − at ground)] [2025/20m/4a]

3. Calculate the forward current caused by 0.8 V forward voltage across the diode with ideality factor of semiconductor material as 1. The reverse saturation current of diode is $12.674\times {10}^{-13}A$ at a temperature of 22°C. [Assume Boltzmann constant $K=1.38\times {10}^{-23}J{K}^{-1}$, charge of electron $q=1.6\times {10}^{-19}C$]. [2022/10m/1b]

4. Two ideal and identical junction diodes are connected as shown in Fig. 1(d). If the current through the reverse-biased diode is $I_0$ and is constant, explain the circuit operation when both the diodes are connected in forward-biased condition. Assume $V_T=25mV$, $V_{\gamma }=0.7V$ and $\eta =1$ for the diodes.

[Figure: Fig. 1(d): Single series loop: a battery $V$ = 50 mV in the bottom branch (longer plate, i.e. + terminal, on the left side); the top branch contains two diodes in series, $D_1$ (left, voltage $V_1$ marked above it) and $D_2$ (right, voltage $V_2$ marked above it), connected back to back: $D_1$ drawn with its arrow pointing left (cathode towards the left, anode joined to $D_2$) and $D_2$ drawn with its arrow pointing right (anode joined to $D_1$, cathode towards the right); the left and right vertical wires close the loop to the battery terminals] [2016/10m/1d]

5. Silicon diodes $D_1$ and $D_2$ in the circuit of the figure given below have saturation current of 1 nA and 20 nA, respectively, at 300 K. Find $i_1$, $i_2$, $V_1$ and $V_2$ Given Boltzmann constant $k=1.38\times {10}^{-23}$ J/K, electronic charge $q=1.6\times {10}^{-19}$ C and emission coefficient n = 1 for Ge and 2 for Si.

[Figure: Single series loop: 6 V battery on the left (+ at top); current $i_1$ flows right along the top wire through diode $D_1$ (anode on the left, cathode on the right; voltage $V_1$ across it, + on the left, − on the right); then down the right-hand side through diode $D_2$ drawn pointing upwards (anode at the bottom, cathode at the top; voltage $V_2$ across it, − at the top, + at the bottom; current $i_2$ marked upwards); the bottom wire returns to the − terminal of the battery] [2006/5m/1b(iii)]

6. “Measurement of Hall-Coefficient reveals the sign of charge carriers, thus giving type of conductivity and the concentration of charge carriers”, Explain the ‘Hall-Effect in D-type [?] semiconductors. Hence define Hall-Coefficient. [2006/20m/5a]

7. Draw the small signal model of FET. Define $\mu$, $g_m$ and $r_d$, and obtain relationship between them. [2005/5m/4a(iii)]

8. Explain varactor diode. Give its equivalent circuit. Give its application. [2005/10m/6c(ii)]

9. Describe the band structure of an open-circuited P-N junction. [2004/20m/7a]

10. Describe the factors on which the conductivity of intrinsic semiconductor depends. A semiconductor is made of ‘n’-type germanium. From the following data, calculate the conductivity of ‘n’-type germanium: (i) Density of Ge = $5.32\times {10}^{3}kg/m^3$ (ii) At. wt. of Ge = 72.6 kg/k.mol (iii) Charge of electron = $1.6\times {10}^{-9}$ C (iv) Mobility of holes = $0.18m^2/V.s$ (v) Mobility of electrons = $3.8m^2/V.s$ (Assume one donor atom in each ${10}^8$ atoms) [2003/20m/4a]

11. What is the proportion in which n-type and p-type Si both having conductivity of $10oh{m}^{-1}{m}^{-1}$ be mixed so as to produce a fully compensated semiconductor at room temperature? Mobility of electrons and holes in Si are 0.14 and $0.05m^2{V}^{-1}{s}^{-1}$ respectively at room temperature. [2001/20m/3a]

12. The conductivity of intrinsic Si at room temperature is $3.3\times {10}^{-4}oh{m}^{-1}{m}^{-1}$. A bridge is available which can measure 1 in ${10}^4$ changes in resistance. With what accuracy can this Si be used to measure the temperature in the range from 0°C to 100°C? The energy band gap in Si is 1.1 eV. The Boltzmann constant, $k=1.38\times {10}^{-23}J{K}^{-1}$ and the electronic charge, $e=1.6\times {10}^{-19}$ C. [2001/20m/6a]

13. Describe the constructional features of E-MOSFET. Calculate the voltage gain from gate to drain of the circuit shown in the above figure.

[Figure: E-MOSFET amplifier, $g_m=4000\mu \mho$: a.c. source (one terminal grounded) through a 1 MΩ resistor to the gate; 100 MΩ resistor from the gate to ground; drain connected through 12 kΩ to +20 V; source connected to ground through an unbypassed 400 Ω resistor; drain coupled through a capacitor to a 48 kΩ [?] load resistor to ground] [1999/20m/8a]

14. Draw a simple experimental set up to measure the Hall effect and show that the Hall field can be written as $E_y=V_X{B}_Z$ where $V_X$ and $B_Z$ are the applied voltage and magnetic fields respectively. What are the typical applications of Hall effect? [1998/20m/1d]

15. Explain the concept of Fermi-level. Sketch the Fermi-energy level for an n-type semi conductor as a function of temperature beginning at $T=0^{\circ }$K and going to a very “high” temp. Qualitatively discuss the nature of the characteristic. [1998/20m/4a]

16. Consider the set up shown in the figure below for measuring Hall effect. Assume that $L={10}^{-1}$ cm, $W={10}^{-2}$ cm. The following parameters are measured: $I_X=1.0$ mA, $V_X=12.5$ V $B_Z=5\times {10}^{-2}$ T, $V_H=-6.2$ mV Find the type of the semiconductor, majority carrier concentration and the mobility.

[Figure: Hall-effect set-up: rectangular semiconductor bar of length L (along x, between the current contacts), width W and thickness d, lying in the x–y plane; voltage $V_x$ (battery, + and − marked) drives current $I_x$ along the length; magnetic field $B_z$ perpendicular to the bar; Hall voltage $V_H$ (+ and − marked) measured across the width; fields $E_x$ and $E_H$ and the carrier drift marked inside the bar] [1998/20m/8a]

17. What do you understand by the forbidden gap in energy bands? Electrons are excited across the forbidden energy gap $E_0$ in Germanium by bombarding of photons. Calculate the maximum wavelength for a photon which will produce electron-hole pairs in Germanium, if $E_0=0.71$ eV. [1997/20m/5c]

18. The bulk n-type region of a particular Germanium junction has conductivity of ${10}^4$ S/m at 300 K and that the for the p-region is ${10}^2$ S/m. Find the voltage drop across the junction in equilibrium at 300K, assuming intrinsic carrier concentration as $2.5\times {10}^{19}{m}^3$ mobility of electron and holes as $0.36m^2/v\mathrm{\text{–}}s$ and $0.17m^2/v\mathrm{\text{–}}s$ respectively. [1997/20m/8c]

19. Calculate the conductivity of silicon when it is doped by an n-type impurity to the extent of 1 in ${10}^6$. The atomic density of silicon is $5\times {10}^{22}atoms/c{m}^3$, the intrinsic carrier density is $1.48\times {10}^{10}pair/c{m}^3$ and the mobilities are $500c{m}^2/V\mathrm{\text{–}}s$ and $1300c{m}^2/V\mathrm{\text{–}}s$. Compare the conductivity with that of intrinsic silicon. [1995/20m/5c]

20. Find the CB h-parameters of a transistor in terms of its r-parameters and α. [1995/20m/8a]

21. What is MESFET? Give its characteristics. What are intrinsic and extrinsic parameters of a MESFET? What is the effect of increasing the channel doping to a value as high as possible? [1995/20m/11b]

4.2] Diode circuits

14 questions

1. A single-phase, full-wave bridge diode rectifier supplied from 240 V, 50 Hz AC source is feeding a resistive load $R_L=100\Omega$ as shown in the figure below. Due to fault in the diode $D_2$, it behaves like a resistance of $1k\Omega$. Sketch the load voltage, load current and source current waveforms under faulty condition. Also calculate the load average voltage and r.m.s. source current under this situation:

[Figure: Single-phase diode bridge: left leg $D_1$ (upper) and $D_4$ (lower), right leg $D_3$ (upper) and $D_2$ (lower); all four diodes point upward (anode below, cathode above). One terminal of the 240 V, 50 Hz AC supply goes to the junction of $D_1$ and $D_4$, the other to the junction of $D_3$ and $D_2$. Top rail (cathodes of $D_1$, $D_3$) to the top of $R_L=100\Omega$; bottom rail (anodes of $D_4$, $D_2$) to the bottom of $R_L$] [2026/10m/4b(ii)]

2. Draw the output voltage waveform of the circuit given below for 5 V, 50 Hz ac rms input. Forward voltage drop in diode $D_1$ is 0.6 V.

[Figure: Two-port circuit, INPUT terminals on the left, OUTPUT terminals on the right, common lower line. Capacitor $C_1=100\mu F$ in series in the upper line (− plate on the input side, + plate on the output side). After $C_1$: $R_1=10K$ from the upper line to the lower line; and a branch from the upper line to the lower line consisting of diode $D_1$ (cathode at the upper line, anode downward) in series with a 3 V battery (+ terminal towards the diode’s anode, − terminal at the lower line). The output is taken between the upper and lower lines] [2025/10m/1c]

3. (i) Find the value of average current flow through the load resistor for the circuit given in Fig. 6(a). (ii) Find the value of r.m.s. current drawn from the source.

[Figure: Fig. 6(a): Single-phase diode bridge. Left leg: $D_3$ (lower) and $D_1$ (upper) in series, both with anode below and cathode above; right leg: $D_4$ (lower) and $D_2$ (upper) in series, same orientation. Source $v\left(t\right)=320sin\omega t$, $\omega =2*\pi *50$, connected with one terminal to the junction of $D_1$ and $D_3$ and the other terminal (wire crossing without connection) to the junction of $D_2$ and $D_4$. The cathodes of $D_1$ and $D_2$ (top rail) connect through a 320 kΩ resistor in series with a 160 V battery (positive plate towards the resistor/top rail) to the anodes of $D_3$ and $D_4$ (bottom rail)] [2017/20m/6a]

4. Draw a circuit diagram for a single-phase, full-wave, midpoint diode rectifier. Sketch waveforms for source voltage, load voltage, voltage across one diode and source current. Take turns ratio from each secondary to primary as unity. Derive expressions for average and r.m.s. output voltages. [2010/10m/1c(i)]

5. Determine the reading of the ideal voltmeter connected across a silicon diode shown in Fig. 9: Assume the forward voltage of diode to be 0.7 V. Find also the current through the diode.

[Figure: Fig. 9 – Series loop: 5 V battery (+ at top) – 1 K resistor – silicon diode D (anode on the resistor side, cathode on the right, i.e. forward biased by the battery) – back along the bottom line (grounded) to the − terminal; ideal voltmeter V connected directly across the diode] [2010/4m/5b(ii)]

6. Construct circuits using diodes which exhibit terminal characteristics as shown in Part (i) and Part (ii) of the figure below. Assume diodes to be ideal.

[Figure: Two I–V characteristics. Part (i): $I=0$ for $-V_1\le V\le V_1$; for $V>V_1$ a straight line of positive slope rising from $(V_1,0)$; for $V<-V_1$ a straight line of positive slope falling from $(-V_1,0)$ into negative current. Part (ii): vertical jump at $V=0$ from $-I_1$ to $I_1$ (along the I-axis); for $V>0$ a straight line of small positive slope starting at $(0,I_1)$; for $V<0$ a straight line of small positive slope ending at $(0,-I_1)$] [2009/20m/3a]

7. Input voltage to the circuit of the figure given below is $v_{in}=12sint$ V. Determine the output voltage $v_0$ and sketch it, What is the name of the circuit?

[Figure: a.c. source $v_{in}$ (+ at top); 1 kΩ resistor in the top wire from the source to node N; from node N to the bottom wire a series branch: 3 V battery (− terminal at node N, + terminal below) followed by diode D (cathode towards the battery, anode at the bottom wire); 3 kΩ load resistor from node N to the bottom wire, output $v_0$ across it (+ at top)] [2006/5m/2a(iv)]

8. Draw the circuit diagram of a half wave rectifier with a reservoir capacitor that smooths the output. Draw its output waveform. Determine the reservoir capacitor value for a HWR and smoothing circuit to supply 20 V to a load of 500 Ω. Maximum ripple amplitude is to be 10% [?] of the average output voltage, and the input signal frequency is 50 Hz. [2004/20m/7a]

9. .

(i) Calculate the quiescent collector current $I_{CQ}$ or room temperature for the amplifier circuit shown in the figure given below.

[Figure: Voltage-divider-biased npn transistor amplifier: supply (10 ± 1) V on the top line; 4.2 k from the supply to the base node and 0.4 k from the base node to ground (the base node connected to the base); collector resistor 0.3 k from the supply to the collector; emitter resistor (100 ± 10) Ω from the emitter to ground.] [2000/10m/4b(i)]

(ii) Describe the applications of clipping and clamping circuits. [2000/10m/4b(ii)]

10. The figure below shows a full wave rectifier circuit. For a sinusoidal input voltage, plot the voltage wave forms across R and $D_1$. [1998/20m/4b]

11. Select any Three of the following statements, read them carefully and identify correct and incorrect ones. Justify your answer using not more than 200 words in each case: The required PIV capacity of diodes in single phase bridge rectifier is one half than that required in rectifier using centre tap transformer. [1998/20m/200w/1d]

12. For full-wave rectification, what circuit configuration would be preferred and why? A bridge rectifier fed through a transformer from a 230 V, 50 Hz supply is used to deliver power to a transistor radio at 9V d-c. Assuming ideal diodes and load resistance of 90 Ω, specify the turns-ratio and current rating of transformer. Also find the d-c and a-c (rms) values of Load current and Peak-Inverse-Voltage. [1997/20m/4b]

13. In the circuit of Fig. 5a, the diode is ideal, $R=1.2k\Omega$ and $I=5$ mA. Draw the v – i characteristics of the circuit (i) with S open and $-10$ volt $<v<$ 15 volt and (ii) with S closed and $0<v<$ 15 volt What happens when $v<0$ with S closed?

[Figure: Fig. 5a: Four branches in parallel between a top line and a bottom line: (1) voltage source v (+ at top), with current i marked in the top line leaving its + terminal; (2) switch S in series with an ideal diode, cathode towards S (top) and anode at the bottom line; (3) resistor R; (4) current source I (arrow upwards)] [1996/20m/5a]

14. In the circuit of Fig. Q 5(b), the diodes are ideal. Determine and sketch $v_0\left(t\right)$ for $0<t<8$ ms when $v_1\left(t\right)$ is a square waveform of ± 1 V amplitude, 8 ms period with a positive going zero crossing at $t=0$, the input $v_2\left(t\right)$ 2 sin πt/3 volt with t in ms and $v_3\left(t\right)$ is a 3 V amplitude rectangular pulse existing over 1 ms $<t<$ 3 ms.

[Figure: Fig. Q 5(b): Three inputs $v_1\left(t\right)$, $v_2\left(t\right)$ and $v_3\left(t\right)$, each connected to the anode of an ideal diode; the three cathodes are joined to a common node, which is connected to ground through resistor R; output $v_0\left(t\right)$ taken from the common node] [1995/20m/5b]

4.3] Biasing and bias stability

17 questions

1. For the circuit shown in the figure below, the two transistors $Q_1$ and $Q_2$ have ${\beta }_1=35$ and ${\beta }_2=30$. The resistance $R_2$ is variable. The output voltage $V_o$ across resistance $R_o$ is $+5.0V$. If the voltage $V_{CC}$ is kept at $+12.0V$, find the value of $R_2$. Derive any formula used. Assume $V_{BE}=0.7V$ for both the transistors:

[Figure: Darlington pair of NPN transistors. Supply rail $V_{CC}=+12.0V$. $R_1=100K$ from $V_{CC}$ to the base of $Q_1$; variable resistor $R_2$ from the base of $Q_1$ to ground. Collectors of $Q_1$ (${\beta }_1$) and $Q_2$ (${\beta }_2$) both connected to $V_{CC}$. Emitter of $Q_1$ drives the base of $Q_2$. Emitter of $Q_2$ is the output node $V_o=+5.0V$, with $R_o=1k\Omega$ from the emitter of $Q_2$ to ground] [2026/10m/4b(i)]

2. For the circuit shown below, early voltage $V_A=\infty$ and $\beta =100$. Find the reverse saturation current if: (i) the collector current of $Q_1=0.5mA$. (ii) $Q_1$ is biased at the edge of saturation.

[Figure: $V_{CC}=2.5V$; voltage divider 50 kΩ (from $V_{CC}$ to the base of NPN transistor $Q_1$) and 30 kΩ (from the base to ground); 3 kΩ from $V_{CC}$ to the collector; emitter grounded.] [2023/20m/4a]

3. For the transistor circuit shown in Figure 1(d), determine the value of reverse saturation current, $I_S$, that would give a collector current of 1 mA, if $\beta =80$, $V_A=\infty$ and $V_T=26mV$ at $T=300K$.

[Figure: Figure 1(d): pnp transistor $Q_1$ with its emitter connected to $V_{CC}=2.5V$. The collector is connected through 1.6 kΩ to ground. A 20 kΩ resistor is connected between the base and the collector (base–collector feedback).] [2021/10m/1d]

4. A Darlington transistor pair circuit is shown in Figure 1(d) below. Both the transistors have dc current gain β of 30. In the circuit $V_{CC}=+12V$, $R_E=1.5k\Omega$. (i) Find the value of $R_1$ needed to bias the circuit such that $V_{CE{Q}_2}=5V$ for transistor $T_2$. (ii) With the same value of $R_1$ as obtained above, determine the value of $V_{CE{Q}_1}$. Assume both $T_1$ and $T_2$ are Si transistors.

[Figure: Figure 1(d): Darlington pair of npn transistors $T_1$ and $T_2$. The collectors of $T_1$ and $T_2$ are both connected to the supply rail $V_{CC}$; resistor $R_1$ is connected from the $V_{CC}$ rail to the base of $T_1$; the emitter of $T_1$ drives the base of $T_2$; the emitter of $T_2$ goes through $R_E$ to ground] [2020/10m/1d]

5. Find the DC input resistance at the transistor base of the circuit shown in Figure 1(c).

[Figure: Figure 1(c): npn transistor (current gain ${\beta }_{DC}$) with collector connected through $R_C$ to $+V_{CC}$ and emitter connected through $R_E$ to ground; input voltage $V_{in}$ (+ at top) applied between the base and ground, input current $I_{in}$ flowing into the base; $V_{BE}$ marked between base (+) and emitter (−)] [2019/10m/1c]

6. For the circuit shown in Figure 3(c), derive the expression for stability factor S(β).

[Figure: Figure 3(c): Collector-to-base (collector feedback) bias: npn transistor with collector connected through $R_C$ to $+V_{CC}$; resistor $R_B$ connected from the collector to the base; emitter connected directly to ground] [2019/10m/3c]

7. For the circuit given in Figure 6(d), comment on its operating conditions.

[Figure: Figure 6(d): pnp transistor amplifier with $V_{CC}=-30V$. $R_b=10k\Omega$ from the $V_{CC}$ line to the base (base current $I_B$ shown flowing upward through $R_b$); collector connected to $V_{CC}$ through the primary winding of an output transformer, whose resistance is $R_c=15\Omega$; the transformer secondary feeds the load $R_L$; emitter connected to ground through $R_e=5\Omega$ in parallel with bypass capacitor $C_e$; signal source $V_s$ in series with $R_s$ coupled to the base through capacitor C, the other side of $V_s$ grounded]

For the transistor, β = 100 $I_{CO}=1mA$ (at $V_{CB}=40V$) [2019/10m/6d]

8. Determine $I_D$ and $V_{GS}$ for the JFET with voltage divider bias as shown in Figure 7(b). The internal parameter values of this JFET are such that $V_D\approx 7V$.

[Figure: Figure 7(b): n-channel JFET with voltage divider bias: $V_{DD}=+12V$; $R_1=6.8M\Omega$ from $V_{DD}$ to the gate and $R_2=1.0M\Omega$ from the gate to ground; drain resistor $R_D=3.3k\Omega$ from $V_{DD}$ to the drain (drain current $I_D$ flowing downward; drain voltage $V_D$); source resistor $R_S=2.2k\Omega$ from the source to ground] [2019/10m/7b]

9. With reference to a BJT, show that $\frac{\partial P_c}{\partial T_j}<\frac{1}{{\theta }_{JA}}$ must be satisfied in order to prevent thermal runaway. [2011/15m/1d]

10. For the circuit shown in Fig. 2– 1. determine the operating point; 2. find the stability factor. Given: $V_{BE}=0.6V$, $\beta =50$.

[Figure: Fig. 2 – NPN transistor ($\beta =50$) in voltage-divider bias: $V_{CC}=15$ V; 39 K from $V_{CC}$ to the base, 4.7 K from the base to ground; 4.7 K collector resistor from $V_{CC}$ to the collector; 1 K emitter resistor from emitter to ground; input terminal at the base (other input terminal at ground), output terminal at the collector (other output terminal at ground)] [2010/10m/1b(i)]

11. For the circuit shown in the figure, assume $\beta =h_{FE}=100$.

(i) Find if the silicon transistor is in cut-off, saturation or in the active region. [2009/10m/1b(i)]

(ii) Find $v_o$.

[Figure: PNP transistor Q: collector connected through 3 K to the −10 V supply, output $v_o$ taken at the collector; emitter connected through $R_e=500\Omega$ to ground; base connected through 7 K to the negative terminal of a 3 V battery whose positive terminal is grounded] [2009/5m/1b(ii)]

12. An $n$–$p$–$n$ silicon transistor is used in a common-collector circuit as shown in the figure below. The circuit component values are $V_{CC}=3.0V$, $R_e=1K$, $R_1=R_2=5K$. If $\beta =44$, find the quiescent point.

[Figure: Common-collector (emitter follower) bias circuit: collector connected directly to $V_{CC}=3.0$ V; voltage divider $R_1=5$ K from $V_{CC}$ to the base and $R_2=5$ K from the base to ground; emitter connected through $R_e=1$ K to ground] [2009/12m/6b(i)]

13. For the circuit of the figure given below $\beta =100$, $R_1=90$ kΩ, $R_2=10$ kΩ, $R_C=5$ kΩ, $R_E=1$ kΩ and $V_{CC}=20$ V Determine $i_B$, $i_C$ and $V_{CE}$.

[Figure: Voltage-divider biased NPN transistor: $R_1$ from $+V_{CC}$ to the base node, $R_2$ from the base node to ground; collector through $R_C$ to $+V_{CC}$; emitter through $R_E$ to ground] [2006/5m/7a(iv)]

14. List the three sources of instability of collector current Define the three stability factors. Which biasing arrangement gives you better stability? [2005/5m/2a(iii)]

15. .

(i) Calculate the quiescent collector current $I_{CQ}$ or room temperature for the amplifier circuit shown in the figure given below.

[Figure: Voltage-divider-biased npn transistor amplifier: supply (10 ± 1) V on the top line; 4.2 k from the supply to the base node and 0.4 k from the base node to ground (the base node connected to the base); collector resistor 0.3 k from the supply to the collector; emitter resistor (100 ± 10) Ω from the emitter to ground.] [2000/10m/4b(i)]

(ii) Describe the applications of clipping and clamping circuits. [2000/10m/4b(ii)]

16. The JFET used in the circuit of Fig. 4 (a) has the following data: $R_D=2k\Omega$, $R_S=8k\Omega$ $V_{DD}=15$ V, $V_G=10$ V and $V_{SS}=-8$ V. Assuming $I_{DSS}=5$ A and $V_{PO}=-3$ V for the JFET calculate $V_{GS}$ and $V_O$.

[Figure: Fig. 4 (a): n-channel JFET source follower: drain connected through $R_D$ to $V_{DD}$; gate G driven by the input voltage ($V_G$, + at the gate, − at the common line); source connected through $R_S$ to $V_{SS}$; output $V_O$ taken between the source and the common line] [1997/20m/4a]

17. A silicon transistor has a β-independent bias using an emitter resistor potential divider combination. The emitter circuit resistance is 300 Ω, the collector circuit resistance is 500 Ω, collector supply voltage is 15 V and $\beta =100$. Find the potential divider resistances so that maximum symmetrical swing is permitted at the collector. Take $V_{CE,sat}=0$. [1995/20m/8b]

4.4] Transistor and FET amplifiers

17 questions

1. In the circuit given below, transistors $T_1$ and $T_2$ are having $V_{BE}=0.6V$ and $\beta =499$. (i) Calculate small signal ac voltage gain of the amplifier at 20 Hz and 2 kHz. (ii) Find dc voltages on collectors of transistors $T_1$ and $T_2$ respectively.

[Figure: Two-stage direct-coupled NPN amplifier, $V_{CC}=12V$, common ground rail. INPUT through coupling capacitor $C_1=10\mu F$ (− on input side, + on base side) to the base of $T_1$. $R_1=9.1K$ from $V_{CC}$ to the collector of $T_1$; the collector of $T_1$ is connected directly to the base of $T_2$. $R_2=2K$ from $V_{CC}$ to the collector of $T_2$. Emitter of $T_1$ goes to node E1; $R_5=200E$ (Ω) from E1 to node F; $R_6=1.3K$ from F to ground, bypassed by $C_4=3.3\mu F$ (+ at F) from F to ground. $R_3=36K$ from E1 up to a wire that goes through capacitor $C_2=10\mu F$ (− on the $R_3$ side, + on the collector side) to the collector of $T_2$. Emitter of $T_2$ goes to node E2; $R_7=1K$ from E2 to ground and $C_5=100\mu F$ (+ at E2) from E2 to ground; $R_4=100K$ from E2 back to the base of $T_1$. Collector of $T_2$ through $C_3=100\mu F$ (+ on collector side) to the OUTPUT node; $R_L=10K$ from OUTPUT to ground] [2025/20m/3b]

2. Calculate the lower corner frequency for the circuit shown below. Take transistor parameters as: $\beta =100$, $V_{BE}=0.7V$ and $V_A=\infty$.

[Figure: Common-emitter amplifier, $V_{CC}=12V$. Source $v_i$ (+ at top) in series with $R_S=0.5k\Omega$ and coupling capacitor $C_C=0.1\mu F$ to the base of an NPN transistor. Bias divider: $R_1=10k\Omega$ from $V_{CC}$ to the base, $R_2=1.5k\Omega$ from the base to ground. $R_C=1k\Omega$ from $V_{CC}$ to the collector; output $v_o$ taken at the collector. $R_E=0.1k\Omega$ from the emitter to ground (no bypass capacitor). The − terminal of $v_i$ is grounded.] [2023/10m/1d]

3. A common-emitter amplifier circuit is shown in Figure 3(a). Neglect $r_x$ and $r_o$ and assume the current source to be ideal. (i) Derive an expression for the midband gain. (ii) Derive expressions for the break frequencies caused by $C_E$ and $C_C$. (iii) Give an expression for the amplifier voltage gain $A\left(s\right)$. (iv) For $R_{sig}=R_C=R_L=10k\Omega$, $\beta =100$ and $I=1mA$, find the value of the midband gain. (v) Select values for $C_E$ and $C_C$ to place the two break frequencies a decade apart and to obtain a lower 3 dB frequency of 100 Hz while minimizing the total capacitance. (vi) Sketch a Bode plot for the gain magnitude and estimate the frequency at which the gain becomes unity.

[Figure: Figure 3(a): npn BJT common-emitter stage. Signal source $V_{sig}$ (+ terminal on top, − terminal grounded) in series with $R_{sig}$ drives the base. Collector connected through $R_C$ to $V_{CC}$ (arrow pointing up); collector coupled through capacitor $C_C$ to the output node $V_o$, with load $R_L$ from $V_o$ to ground. Emitter connected to an ideal current source I (arrow pointing down) going down to the negative supply (arrow pointing down), and from the emitter a bypass capacitor $C_E$ to ground.] [2022/20m/3a]

4. The amplifier shown in Figure 4(c) is biased to operate at $I_D=1mA$ and $g_m=1mA/V$. Neglecting $r_o$, (i) determine the midband gain. (ii) determine the value of $C_S$ that places $f_L$ at 10 Hz.

[Figure: Figure 4(c): n-channel MOSFET amplifier. Source $V_i$ (+ terminal on top, − terminal grounded) connected directly to the gate. Drain connected through $R_D=10k\Omega$ to $V_{DD}$ (arrow pointing up); output $V_o$ taken from the drain. Source terminal connected through $R_S=6k\Omega$ down to the negative supply (arrow pointing down), and from the source terminal a capacitor $C_S$ to ground.] [2022/10m/4c]

5. For the circuit shown in Fig. 2(c), calculate the resistance $R_o$ as seen by the output terminals. Ignore the effect of $R_1$ and $R_2$. Assume $\beta =99$ and $h_{ie}=1k\Omega$. Comment on the value of $R_o$ of the circuit:

[Figure: Fig. 2(c): Emitter follower: NPN transistor with collector connected directly to $+V_{CC}$; bias resistor $R_1$ from $+V_{CC}$ to the base and $R_2$ from the base to ground; a.c. source $V_s$ (bottom grounded) connected to the base through a 1 kΩ source resistance (drawn as a coil-shaped element labelled 1 kΩ); emitter connected to ground through a 1 kΩ resistor; output $V_o$ taken at the emitter; an arrow marks $R_o$ as the resistance looking into the emitter/output terminal] [2016/10m/2c]

6. Draw the circuit of a Cascode amplifier. Indicate the two configurations of transistors used. Why is this circuit preferred in high-frequency applications? [2010/6m/2b(i)]

7. Draw the circuit of Darlington emitter follower. Obtain the expressions for overall current gain and input impedance. You can use suitable approximations. Find the above two quantities if $R_B=2M\Omega$, $R_E=1k\Omega$. The device parameters are identical. $h_{f{e}_1}=h_{f{e}_2}=50,h_{i{e}_1}=h_{i{e}_2}=1K,h_{o{e}_1}=h_{o{e}_2}=20\mu A/V$ [2010/10m/3a(i)]

8. Three identical cascaded stages have an overall upper 3-dB frequency of 20 kHz and a lower 3-dB frequency of 20 Hz. What are $f_L$ and $f_H$ of each stage? Assume non-interacting stages. [2009/8m/6b(ii)]

9. The ac equivalent circuit of an N-P-N transistor circuit is shown below. Draw the actual circuit with biasing and coupling capacitors.

[Figure: Input $V_i$ with input current $I_b$ through resistor $h_{ie}$ in the top wire to the output node $V_o$; from the output node to the common bottom wire a current source $h_{fe}{I}_b$ (arrow pointing up, towards the output node) and load resistor $R_L$ in parallel; output $V_o$ taken at the right end of the top wire] [2007/5m/4a(ii)]

10. What is the impedance reflection principle as referred to FET circuits? Draw the circuit of a typical source follower and apply reflection principle to obtain its output equivalent circuit. [2006/5m/5b(iii)]

11. What do you understand by Miller capacitance? For a CE amplifier following parameters are given $r_i=10$ kΩ [?], $C_{b\prime c}=4$ pF, $R_b=1$ kΩ, $C_{b\prime e}=300$ pF, $r_{bb\prime }=20\Omega$, $g_m=0.5$ S, $r_{b\prime e}=150\Omega$, $R_L=300\Omega$ and $R_C\gg R_L$. Determine the Miller capacitance. [2006/5m/8a(iii)]

12. Obtain the voltage gain and output resistance of the composite amplifier shown in Fig. above.

[Figure (printed above the text): Composite FET–BJT follower. Input $v_i$ applied between the input line and the ground (bottom) line; resistor $R_G$ from the input line to ground; the input line goes to the gate of FET $T_1$; drain of $T_1$ to the supply $V_{CC}$ (top line); source of $T_1$ connected to the base of bipolar transistor $T_2$; collector of $T_2$ to $V_{CC}$; emitter of $T_2$ to ground through resistor $R_E$; output $v_o$ taken across $R_E$ (between the emitter and ground).] [2001/20m/4b]

13. The transistor shown in the above figure has following h parameters: $h_{ie}=1000\Omega$, $h_{fe}=50$, $h_{re}=3\times {10}^{-4}$ and $h_{oe}=5\times {10}^{-5}$ Find the voltage gain and ac. input impedance of the amplifier. Neglect capacitor impedances.

[Figure: Common-emitter amplifier, supply +20 V: voltage-divider bias – 60 kΩ from +20 V to the base and 30 kΩ from the base to ground; input $V_{in}$ applied to the base through a coupling capacitor; 10 kΩ collector resistor from +20 V to the collector; 10 kΩ emitter resistor from the emitter to ground, bypassed by a capacitor; output $V_{out}$ taken from the collector through a coupling capacitor across a 30 kΩ load resistor to ground] [1999/20m/6b]

14. Describe the constructional features of E-MOSFET. Calculate the voltage gain from gate to drain of the circuit shown in the above figure.

[Figure: E-MOSFET amplifier, $g_m=4000\mu \mho$: a.c. source (one terminal grounded) through a 1 MΩ resistor to the gate; 100 MΩ resistor from the gate to ground; drain connected through 12 kΩ to +20 V; source connected to ground through an unbypassed 400 Ω resistor; drain coupled through a capacitor to a 48 kΩ [?] load resistor to ground] [1999/20m/8a]

15. For the circuit shown in the figure below, draw the ac. equivalent circuit and find the voltage gain of the amplifier.

[Figure: JFET common-source amplifier: a.c. source (grounded) coupled through capacitor $C_c$ to the gate; gate bias divider $R_1$ from $V_{DD}$ to the gate and $R_2$ from the gate to ground; drain connected through 100 K to $V_{DD}$, output $V_o$ taken at the drain; source grounded; device data $r_d=50K\Omega$, $\mu =300$ [?]] [1998/20m/7b]

16. The mid-band equivalent circuit of a common emitter transistor amplifier is shown in Fig. 4(c). The h-parameters of the transistor used are $h_{ie}=1500\Omega$, $h_{re}={10}^{-3}$, $h_{fe}=100$, $h_{oe}=50\times {10}^{-6}\Omega$ Find the mid-band gain $i_{S_1}/i_{be}$ [?] where $i_{S_1}$ [?] where is the current in 5 kΩ resister.

[Figure: Fig. 4(c) (hand-drawn, partly illegible): input side – signal current source $i_s$ (arrow up) with its source resistance [?] in parallel, feeding terminals B–E through a bias resistance [?]; then $h_{ie}$ in series with a controlled voltage source $h_{re}{v}_{ce}$; output side between C and E – controlled current source $h_{fe}{i}_{be}$ (arrow down), $1/h_{oe}$, the collector resistor $R_c$ = 10 kΩ and the 5 kΩ load (current $i_{S_2}$ [?]) all in parallel; output voltage $v_{ce}$ between C and E] [1997/20m/4c]

17. Find the mid-frequency gain of the amplifier shown in Fig. 8b. Neglect the loading effect of $R_1$ and $R_2$. The transistor parameters with usual notations are $g_m=0.015$ S, $r_{b\prime e}=1\Omega k$, $r_{bb\prime }=90\Omega$, $C_{b\prime e}=20$ pF and $C_{b\prime e}=3$ pF while $R_E=1k\Omega$.

[Figure: Fig. 8b: Emitter follower: input source “IN” coupled through capacitor $C_1$ to the base of an npn transistor; bias divider $R_1$ from $V_{CC}$ to the base and a lower resistor (printed $R_5$, i.e. $R_2$ [?]) from the base to ground; collector connected directly to $V_{CC}$; emitter resistor $R_E$ from the emitter to ground; output “OUT” taken from the emitter through a coupling capacitor, with respect to ground] [1996/20m/8b]

4.5] Differential, feedback and power amplifiers

9 questions

1. In the circuit diagram given here, $T_1$ and $T_2$ are transistors with matched characteristics. The transistor parameters in active region are $\beta =200$ and $V_{BE}=688mV$. Find $V_{CE}$ of transistor $T_2$:

[Figure: Current-mirror circuit with +12 V supply rail at top and grounded bottom rail. 560 Ω from +12 V to the collector of $T_1$; 470 Ω from +12 V to the collector of $T_2$. $T_1$ is diode-connected (its collector tied to its base); the bases of $T_1$ and $T_2$ are connected together. Both emitters go to the grounded bottom rail. NPN transistors.] [2024/10m/1c]

2. Consider the figure of differential pair given below. Neglecting the early effect, determine the change in $V_X$, $V_Y$, $V_X-V_Y$ if (i) $V_{CC}$ rises by $\Delta V$ and $R_{C1}=R_{C2}=R_C$. (ii) $I_{EE}$ experiences a change of $\Delta I$ and $R_{C1}=R_{C2}=R_C$. (iii) $R_{C1}=R_{C2}+\Delta R$.

[Figure: BJT differential pair: NPN transistors $Q_1$ and $Q_2$; $R_{C1}$ from $V_{CC}$ to the collector of $Q_1$ (node X); $R_{C2}$ from $V_{CC}$ to the collector of $Q_2$ (node Y); emitters joined and connected to a current source $I_{EE}$ (arrow down) to ground; both bases connected together to a common-mode source $V_{CM}$ (+ at top) whose − terminal is grounded.] [2023/10m/2c]

3. Shown below (Figure 3(a)) is a differential amplifier with a three transistor active load. Draw the small signal equivalent circuit of its output stage with active load and calculate its small signal differential mode voltage gain. Assume the output impedances of the transistors $Q_1$ to $Q_5$ to be $r_{01}$ to $r_{05}$ respectively. Assume the base currents to be negligible.

[Figure: Figure 3(a): Differential pair of npn transistors $Q_1$ and $Q_2$ with emitters joined and connected to a current source $I_Q$ (arrow downward) to $-V_{CC}$. Base of $Q_1$ driven by a source $\frac{v_d}{2}$ (+ at top) to ground, base current $i_{b1}$ into the base; base of $Q_2$ driven by a source $\frac{v_d}{2}$ (− at top, + at bottom) to ground, base current $i_{b2}$. Active load: pnp transistors $Q_3$ and $Q_4$ with emitters at $+V_{CC}$ and bases tied together; collector of $Q_3$ connected to collector of $Q_1$ (current $i_3$ out of $Q_3$, $i_1=\frac{g_m{v}_d}{2}$ downward into $Q_1$); pnp transistor $Q_5$ with base connected to the $Q_1$/$Q_3$ collector node, emitter connected to the common bases of $Q_3$ and $Q_4$, collector to $-V_{CC}$. Collector of $Q_4$ ($i_4=\frac{g_m{v}_d}{2}$ downward) connected to collector of $Q_2$ ($i_2=\frac{g_m{v}_d}{2}$ upward); this output node is coupled through capacitor $C_C$ (current $i_o$) to the load $R_L$ to ground; output $v_o$ across $R_L$] [2020/20m/3a]

4. Find the efficiency of a class A amplifier shown in Figure. Given that the voltage drop across $R_E$ is 1 V, the signal current swings from −0.5 A to +0.5 A and the DC current is 1 A.

[Figure: Transformer-coupled class A amplifier: input applied to the base of a transistor; collector connected to one end of the primary winding of an output transformer (label “0.5 A” beside the primary); the other end of the primary goes to the supply marked 10 V, 1 A; secondary winding feeds a loudspeaker; emitter connected to ground through $R_E$ (1 V across it) with a bypass capacitor in parallel with $R_E$] [2015/10m/1e]

5. Determine the output current of the Widlar current source; given that $\pm V=\pm 15$ volts, $I_{C_0}={10}^{-14}$ amp., $\beta =200$, $V_T=25$ mV.

[Figure: Widlar current source: p-n-p transistor $Q_1$ (emitter at the top, connected to the +V rail, emitter arrow pointing in) with its base and collector shorted (diode-connected); from the collector of $Q_1$ a 39 kΩ resistor (current $I_{in}$ flowing downwards) to the collector of $Q_2$; $Q_2$ is an n-p-n transistor with base and collector shorted (diode-connected) and its emitter connected to the −V rail; the base of $Q_2$ is connected to the base of $Q_3$; $Q_3$ (n-p-n) emitter goes through a 5 kΩ resistor to −V; the collector of $Q_3$ goes upwards (dotted line) to the load, carrying output current $I_o$ (downwards)] [2012/20m/2c]

6. For the current mirror shown in Fig. 4 (c), determine the emitter current of transistor $Q_3$. (Assume $\beta =100$ and $V_{BE}=0.6$ V)

[Figure: Fig. 4 (c): From ground, current $I$ flows through a 4K7 resistor to node a. Transistor $Q_1$ (n-p-n): collector at node a (current $I_{C1}$), emitter to the −10 V rail, base connected to the horizontal line just right of a (base current $I_{B1}$); current $I_1$ flows along the line from a to the base tap and $I_1\prime$ onward to node b. Transistor $Q_2$ (n-p-n): collector at node b (current $I_{C2}$), emitter to −10 V, base connected to the line just right of b (base current $I_{B2}$); current $I_2$ flows from b along the line, which continues as base current $I_{B3}$ into the base of $Q_3$. $Q_3$ (n-p-n): collector through a 4K7 resistor to +10 V (current $I_{C3}$ downwards), emitter to the −10 V rail (current $I_{E3}$ downwards)] [2011/20m/4c]

7. For the voltage series feedback amplifier shown in Fig. 5, calculate $V_f$, feedback ratio $\beta$, voltage gain without feedback $A_V$ and voltage gain with feedback $A_{V_f}$:

[Figure: Fig. 5 – Source $V_s$ in series with the amplifier input; input voltage of the amplifier block $A_V$ is 5 mV (+ at top input terminal); output $V_o=2$ V across a load resistor; feedback network (dashed box) of 19 K and 1 K in series across the output: 19 K from the upper output terminal to a tap, 1 K from the tap to the lower output line; the voltage across the 1 K is $V_f$, connected in series between the source $V_s$ and the lower input terminal of the amplifier] [2010/6m/2b(ii)]

8. For the class C tuned amplifier shown in the above figure, calculate the maximum load power and the transistor power rating if $V_{CE\left(sat\right)}=0.75$ V.

[Figure: Class C tuned amplifier: a.c. input source (sine wave sketched beside it; + terminal up, other terminal grounded) through a series resistor and a coupling capacitor to the base of an NPN transistor; a resistor from the base to ground; emitter grounded; collector connected to a parallel LC tank (capacitor in parallel with the transformer primary) whose other end goes to the supply +60 V [?]; the primary is coupled through a 2:1 transformer to a 60 Ω load resistor on the secondary] [1999/20m/6a]

9. For the voltage-series-feedback amplifier circuit shown in Fig. 1(d), the open-loop gain A of the OP-AMP varies from 15000 to 20000 as the temperature changes from 25°C to 35°C. Calculate the closed-loop gain at both the extreme temperatures, assuming $R_1=470\Omega$ and $R_f=47k\Omega$. Calculate the percentage change in open-loop and closed-loop gains and explain the results. Assume the source impedance to be zero.

[Figure: Fig. 1(d): Op-amp A (supplies $V_{CC}$ and $-V_{EE}$) used as a non-inverting amplifier: source $V_i$ connected between ground and the non-inverting input; a feedback resistor from the output to the inverting-input node (feedback voltage $V_f$ marked); $R_1$ from that node to ground; load $R_L$ across the output; output voltage $V_o$ across $R_L$] [1997/20m/1d]

4.6] Op-amp circuits and filters

43 questions

1. For the circuit given in the figure below, the input voltage signal is given by $V_{\mathrm{\text{in}}}=1.5sin62.8t+0.5sin188.4t$ volts. Determine the output voltage expression for each input component indicating their magnitude and phases. Derive the frequency domain expression for the output voltage:

[Figure: Op-amp circuit: $V_{\mathrm{\text{in}}}$ through series capacitor $C=1.0\mu F$ to the non-inverting (+) input; $R_1=10K$ from the + input node to ground. Inverting (−) input: $R_2=22K$ from the − input to ground and feedback resistor $R_3=10K$ from the output $V_o$ to the − input. Output $V_o$] [2026/10m/5a]

2. Define input bias current and input offset voltage for an OPAMP. Using an OPAMP, draw an inverting amplifier circuit with gain $=-4$ in such a way that the effect of bias current is minimized. [2024/10m/4b(i)]

3. An inverting Op-Amp circuit is to be designed such that the weighted sum $v_0=-(v_1+4v_2)$. Resistors $R_1$, $R_2$ and $R_f$ are to be chosen in a way that for a maximum output voltage of 4 V, the current in the feedback resistor does not exceed 1 mA.

[Figure: Inverting summing amplifier: input $v_1$ through $R_1$ and input $v_2$ through $R_2$ to the inverting (−) input of the op-amp; feedback resistor $R_f$ from the output $v_0$ to the inverting input; non-inverting (+) input grounded.]

Calculate the values of $R_1$, $R_2$ and $R_f$. [2023/10m/3c]

4. An op-amp circuit is shown in Figure 1(d) below. Assume the op-amp to be ideal. (i) Determine $I_1$, $I_2$, $I_3$ and $V_X$. (ii) If $V_o$ is not to be lower than – 13 V, calculate the maximum allowed value for $R_L$. (iii) If $R_L$ is varied in the range 100 Ω to 1 kΩ, what is the corresponding change in $I_L$ and in $V_o$?

[Figure: Figure 1(d): Ideal op-amp, non-inverting (+) input grounded. A 1 V source (+ terminal on top, − terminal grounded) feeds the inverting (−) input through a 10 kΩ resistor carrying current $I_1$ (arrow towards the op-amp). From the inverting-input node a wire rises to a top branch: a 10 kΩ resistor carrying current $I_2$ (arrow to the right) to node $V_X$. From node $V_X$ a 100 Ω resistor goes down to ground, with current $I_3$ marked by an arrow pointing upward (from ground towards $V_X$). From node $V_X$ a variable resistor $R_L$ carrying current $I_L$ (arrow to the right) goes to the right and down to the op-amp output terminal $V_o$.] [2022/10m/1d]

5. Explain what happens when a circuit shown in Figure 3a(i) below is constructed using logarithmic amplifier.

[Figure: Figure 3(a)(i): $V_{REF}$ through $R_1$ to the inverting (−) input of an op-amp; non-inverting (+) input grounded. npn transistor $Q_1$: base grounded, collector connected by a feedback wire to the inverting input, emitter connected to the op-amp output node $V_1$. npn transistor $Q_2$: base connected to $V_1$, collector current $I_X$ (arrow into the collector), emitter connected to the − terminal of a battery whose + terminal is grounded.] [2021/10m/3a(i)]

6. Explain what happens if the topology is modified as shown in Figure 3(a)(ii) below.

[Figure: Figure 3(a)(ii): Same op-amp and $Q_1$ arrangement as Figure 3(a)(i) ($V_{REF}$ through $R_1$ to the inverting input, + input grounded; $Q_1$ base grounded, collector to the inverting input, emitter to the output node $V_1$). npn transistor $Q_2$ now has its base grounded, its emitter connected to $V_1$ and collector current $I_X$ (arrow into the collector).] [2021/10m/3a(ii)]

7. Determine the closed loop gain of the inverting amplifier shown in Figure 4(c) below. Explain the result if $R_1\to 0$ or $R_3\to 0$.

[Figure: Figure 4(c): Op-amp with $A_0=\infty$, non-inverting (+) input grounded. $V_{in}$ (+ terminal on top, − terminal grounded) through $R_2$ to the inverting (−) input. T-network feedback: from the inverting input, $R_3$ to node $V_x$; $R_4$ from node $V_x$ to ground; $R_1$ from node $V_x$ to the output $V_{out}$.] [2021/10m/4c]

8. A first order low pass filter circuit is shown in Figure 4(c) below. It is desired that the dc gain of the filter be 5 and the input impedance is 10 kΩ. The value of the capacitor C = 100 nF. Find the values of R, $R_1$ and the cut-off frequency $f_c$ of the filter. (Assume ideal OP-AMP)

[Figure: Figure 4(c): Inverting op-amp low-pass filter: input $V_i$ through $R_1$ to the inverting (−) input; non-inverting (+) input grounded; feedback from output $V_o$ to the inverting input through R in parallel with C = 100 nF] [2020/10m/4c]

9. Determine the output voltage of the op-amp differentiator circuit shown in Figure 2(c) for the triangular wave input as shown and draw the output voltage waveform.

[Figure: Figure 2(c): Input triangular wave against t: −10 V at t = 0, rising linearly to +10 V at t = 10 μs, falling linearly to −10 V at t = 20 μs, then rising again (peaks +10 V, troughs −10 V, period 20 μs). Differentiator: input through a 0.001 μF capacitor to the inverting (−) input of an op-amp; feedback resistor $R_f=2.2k\Omega$ from the output $V_o$ to the inverting input; non-inverting (+) input grounded] [2019/10m/2c]

10. For the op-amp circuit shown in Figure 1(d), determine the gain $A_v=\frac{v_o}{v_i}$. Assume that all resistors are equal.

[Figure: Figure 1(d): Op-amp with non-inverting (+) input grounded. Input $v_i$ connected through resistor R (current i flowing towards the op-amp) to the inverting (−) input. Feedback network from the inverting input to the output $v_o$: a chain of three series resistors R – R – R; at the junction between the first and second R a resistor R goes to ground, and at the junction between the second and third R another resistor R goes to ground; the third R connects to the output $v_o$. All resistors are R] [2018/10m/1d]

11. The integrator circuit shown in Figure 4(c) is to be used to generate a triangular waveform from a 500 Hz square wave connected to its input. Suppose that the square wave alternates between ± 12 V. (i) Find the minimum slew rate required for the amplifier. (ii) Find the maximum output voltage the amplifier can generate.

[Figure: Figure 4(c): Op-amp integrator: square-wave input applied through a 400 Ω resistor to the inverting (−) input; feedback from output $v_o$ to the inverting input is a 4.7 kΩ resistor in parallel with a 1 μF capacitor; the non-inverting (+) input is connected to ground through a 370 Ω resistor; output terminal $v_o$] [2018/10m/4c]

12. Calculate the output voltage $v_o$ in terms of the input voltages $v_{i_1}$, $v_{i_2}$, $v_{i_3}$ and $v_{i_4}$ for the circuit shown in Figure 8(b).

[Figure: Figure 8(b): Op-amp summing (difference) amplifier. Input $v_{i_1}$ through $R_1$ and input $v_{i_2}$ through $R_2$ join at the inverting (−) input; feedback resistor $R_F$ from the output $v_o$ to the inverting input. Input $v_{i_3}$ through $R_A$ and input $v_{i_4}$ through $R_B$ join at the non-inverting (+) input, which is connected to ground through $R_C$. Output terminal $v_o$] [2018/20m/8b]

13. For the circuit given in Fig. 1(d)– (i) draw the input and output waveforms; (ii) find the average value of the output voltage waveform. Assume that the diode in the circuit is ideal.

[Figure: Fig. 1(d): Op-amp supplied from +15 V and −15 V, output $V_o$. AC source $v\left(s\right)=sin\omega t$, $\omega =2*50*\pi$: its upper terminal connects through a 660 Ω resistor to the non-inverting (+) input; its lower terminal is connected to ground. From the ground node a 1 kΩ resistor in series with a diode (anode towards the 1 kΩ resistor, cathode towards the op-amp) connects to the inverting (−) input; a 2 kΩ feedback resistor connects the inverting input to the output $V_o$] [2017/10m/1d]

14. (i) Draw the circuit diagram of a bandpass filter using OP-AMP. Its parameters are $f_L=300$ Hz, $f_H=2$ kHz and passband gain is 4. (ii) Calculate the value of Q. Assume that the capacitor value is $0.01\mu F$. [2017/20m/8b]

15. For the circuit shown in Fig. 3(c), get the expression for $V_o$. Also sketch the output waveform. Assume that the op-amp is ideal. $R=\sqrt{\frac{L}{C}}$, $\omega =\frac{1}{\sqrt{LC}}$ and $V_i=10sin\omega t$:

[Figure: Fig. 3(c): Inverting op-amp circuit: input $V_i$ → resistor $R$ in series with capacitor $C$ → inverting (−) input; feedback path from output $V_o$ to the inverting input consisting of inductor $L$ in series with resistor $R$; non-inverting (+) input grounded] [2016/10m/3c]

16. For the op-amp circuit shown in Fig. 4(c), deduce the output voltage expression. Calculate $V_o$, when $R_1=1k\Omega =R_2$, $R_3=1K$ and $R_4=2K$ and $V_{in}=1V$:

[Figure: Fig. 4(c): Op-amp circuit: input $V_{in}$ drives two branches: $R_1$ to the inverting (−) input and $R_2$ to the non-inverting (+) input; $R_3$ from the non-inverting input to ground; feedback resistor $R_4$ from the output $V_o$ to the inverting input] [2016/10m/4c]

17. In the Figure shown what is the function of $R_0$ and determine its value when $V_0=-3V_1-2V_2$.

[Figure: Op-amp summing amplifier: input $V_1$ through $R_1$ and input $V_2$ through $R_2$ to the inverting (−) input; feedback resistor 6 kΩ from the output $V_0$ to the inverting input; non-inverting (+) input connected through $R_0$ to the common bottom line, which runs between two open terminals (no ground symbol drawn)] [2015/10m/1d]

18. (i) Why the output voltage of an Op-Amp does not respond immediately to the fast-changing input? (ii) Develop the expression for the slew rate of Op-Amp. (iii) An open-loop configuration of Op-Amp 741C changes its output from +14 V to –14 V each time its input crosses zero volt. If 741C has a typical slew rate of $0.5V/\mu s$, calculate the time between the zero crossings and the maximum frequency at which the output will be distorted. [2014/20m/4a]

19. Design an amplifier with a gain of +5 using one OP-AMP. Choose $R_i=10k\Omega$. [2013/10m/1d]

20. Define the following parameters for an OP-AMP: Input offset voltage; Bias current; Slew rate; Output impedance; CMRR. [2013/5m/1e(ii)]

21. Using an OP-AMP, design a lossy integrator whose peak gain is 20 dB and the gain is 3 dB down from its peak when $\omega =10000$ rad/sec. Use a capacitance of 0.01 μF. [2013/20m/4a]

22. Design a second-order low-pass Butterworth filter having a cutoff frequency of 1 kHz. Choose $C=0.1\mu F$. The damping factor $\alpha$ is given to be 1.414. Choose $R_i$ as 10 kΩ. [2013/20m/4c]

23. Assuming ideal op-amps, determine the expression for the input impedance of the given circuit and a simple passive equivalent of the circuit looking into terminal ①.

[Figure: Terminal ① (+) and a lower return terminal (−) with $V_{in}$ between them and input current $i_{in}$ flowing into terminal ①. Terminal ① is connected to the non-inverting (+) input of op-amp 1, whose inverting (−) input is tied to its own output (voltage follower). The output of op-amp 1 goes through capacitor $C_o$ to a node X; resistor $R_1$ is connected from X to the lower (−) terminal line. Node X is connected to the non-inverting (+) input of op-amp 2, whose inverting (−) input is tied to its own output (voltage follower). Resistor $R_2$ is connected between terminal ① (input line) and the output of op-amp 2] [2012/12m/1e]

24. Draw the circuit of an opamp integrator. Sketch the output waveform, when the input is a symmetrical square wave of amplitude $\pm 3$ V and the repetition frequency is 1 kHz. [2010/4m/5b(i)]

25. Design an opamp second-order Butterworth low-pass filter (LPF) for a cut-off frequency of 2 kHz. Compare the response curve with that of first-order LPF. [2010/10m/6b(i)]

26. With OP-AMP draw a circuit of a unity gain amplifier having no phase shift and give its one practical application. [2007/5m/8a(ii)]

27. Draw the circuit of a two input adder with OP-AMP and explain its operation. [2007/5m/8a(iii)]

28. The ideal op-amp circuit of the figure given below converts voltage $v_i$ into a current $i_L$. Show that if $2R_1=2R_2=R_3+R_4$ and $R_4-R_1=500\Omega$ then $i_L=+v_i$ mA.

[Figure: Op-amp: input $v_i$ through $R_1$ to the inverting (−) input; $R_2$ from the output $v_o$ to the inverting input; $R_3$ from the output $v_o$ to the non-inverting (+) input; $R_4$ from the non-inverting input to ground, carrying the load current $i_L$ (downwards) with voltage $v_L$ across it (+ at top)] [2006/10m/3a(iii)]

29. Design a second-order active RC band-pass filter with a mid-band voltage gain $-A_0=34$ dB, carrier frequency 160 Hz and 3 dB bandwidth 16 Hz. Assume $C_1=C_2=0.1\mu F$. [2005/10m/1b(ii)]

30. The 741C op-amp having the following parameters is connected as shown in the figure. A = 20000, $R_i=2M\Omega$, $R_0=75\Omega$, $f_0=5$ Hz, supply voltage = ±15 V, output voltage swing ±13 V. Identify the circuit. Compute the values of $A_F$, $R_{IF}$, $R_{OF}$, $f_F$ & $V_{OUT}$

[Figure: 741C op-amp with supplies $V_{CC}$ and $V_{EE}$; input source $v_{in}$ between the non-inverting (+) input and ground; 1 kΩ resistor from the inverting (−) input to ground and 10 kΩ feedback resistor from the output to the inverting input; load $R_L$ from the output $v_o$ to ground.] [2005/10m/5b(i)]

31. Draw the circuit diagram of voltage-to-current converter with floating load using op-amp. Derive the necessary equation. [2005/5m/8a(iii)]

32. Design a second-order Butterworth low-pass filter with cut off frequency of 1 kHz [?]. Use only Sallen and Key network configuration as shown below:

[Figure: Sallen–Key low-pass filter: $V_{in}$ through resistor R to node A; from A a second resistor R to the non-inverting (+) input of the op-amp; capacitor C from the + input to ground; a second capacitor C from node A to the op-amp output (feedback); resistor $R_1$ from the inverting (−) input to ground and resistor $R_2$ from the output to the inverting input; output $V_{out}$.] [2004/8m/6a(i)]

33. The following two amplifier circuit is a generalized immitance converter (GIC). Analyze the above circuit to get an expression for $Z_{in}$. Assume the two op-amps to be ideal.

[Figure: Five impedances: $Z_1$, $Z_2$, $Z_3$, $Z_4$ connected in series in a horizontal chain starting at the upper input terminal (nodes: input node, node A between $Z_1$ and $Z_2$, node B between $Z_2$ and $Z_3$, node C between $Z_3$ and $Z_4$, node D after $Z_4$); $Z_5$ from node D down to the lower input terminal (bottom wire). Op-amp OA1 (drawn above the chain): + input to the input node, − input to node B, output to node C. Op-amp OA2 (drawn below the chain): − input to node B, + input to node D, output to node A. $Z_{in}$ is the impedance looking into the two input terminals (arrow).] [2003/10m/2a(i)]

34. With $Z_1=R_1$, $Z_3=R_3$, $Z_2=1/C_{2}s$, $Z_4=R_4$ and $Z_5=R_5$, what does the GIC circuit above realize? [2003/2m/2a(ii)]

35. $Z_1$ and $Z_5$ are capacitors, $Z_2$, $Z_3$ and $Z_4$ are resistors. How does the input impedance $Z_{in}$, behave? [2003/2m/2a(iii)]

36. Consider the op-amp circuit shown.

[Figure: Op-amp circuit: input $v_i$ through resistor $R_1$ to the inverting (−) input; feedback resistor $R_2$ from the inverting (−) input node to the output $v_o$; the non-inverting (+) input connected to ground through an unlabelled resistor.]

In the circuit make the usual assumption that (i) the inverting and non-inverting terminals are virtually at the same potential and (ii) the op – amp does not take any input current at its terminals. You would arrive at the normal conclusion that $v_0=-\frac{v_i}{R_1}.R_2$. Is this conclusion valid? If yes give reasons why operational amplifiers are never used in this manner with inverting input grounded and input to be amplified given to the non-inverting terminal. [2002/20m/5a]

37. The above figure shows the circuit of a voltage follower. Calculate its closed loop voltage gain, input impedance and output impedance. Determine also the output offset voltage. The parameters of 741 C are: Open loop gain $A_{OL}={10}^5$, $r_{in}=2M\Omega$, $r_{out}=75\Omega$, $V_{in}\left(off\right)$ 2mV, $I_{in}$ (bias) = 80 nA and $I_{in}\left(off\right)$ = 20 nA.

[Figure: Voltage follower using a 741 C op-amp: a.c. signal source (+ terminal up, other terminal grounded) connected through a 33 KΩ resistor to the non-inverting input; output $V_{OUT}$ connected directly back to the inverting input] [1999/20m/5a]

38. Select any three of the following statements, read them carefully and identify correct and incorrect ones. Justify your answer using not more than 200 words in each case: An operation amplifier has features suitable for radio frequency timers. [1999/20m/200w/1d]

39. Select any three of the following statements and indicate with justification whether they are correct or incorrect. Your answer must not exceed 200 words for each statements: The characteristic of a twin–T network is similar to that of a notch filter in audio frequency range. [1999/20m/200w/9a]

40. Find the output voltage in steady state condition for the operational amplifier shown in the figure below when (i) switch S is open, (ii) switch S is closed.

[Figure: Inverting op-amp circuit: input $V_i$ through a resistor R to the inverting (−) input; non-inverting (+) input grounded; feedback network from the inverting input: a resistor R to an intermediate node, and from that node to the output $V_o$ two parallel paths – a resistor R, and a switch S in series with a capacitor C] [1998/20m/1b]

41. Explain the working of a timer using general purpose OP AMP IC 741. Design such a timer for a time period of 60 seconds. [1998/20m/4a]

42. Explain the following terms as referred to an operational amplifier: (a) Input offset voltage and (b) Input offset current. [1996/10m/5d(i)]

43. Find the relation between $v_o$ and $v_s$ for the circuit of Fig. 8a and show that, with proper adjustments, the voltage $v_0$ can be made proportional to the logarithm of the input voltage $v_s$.

[Figure: Fig. 8a: Input $v_s$ (+) applied through a resistor to the inverting input of op-amp $A_1$, whose non-inverting input is grounded; transistor $Q_1$ (base grounded) in the feedback path of $A_1$, its collector joined to the inverting input and its emitter joined (dashed line) to the node after resistor R, which is in series with the output of $A_1$; this node also goes to the emitter of transistor $Q_2$; the collector of $Q_2$ is connected through $R_2$ [?] to $V_R$ and, together with the base lead of $Q_2$ [?], to the non-inverting (+) input of op-amp $A_2$; $A_2$ is a non-inverting amplifier with $R_4$ from its output to its inverting input and $R_3$ from the inverting input to ground; output $v_o$ (wiring around $Q_2$ partly unclear in the source)] [1996/20m/8a]

4.7] Oscillators and wave-shaping circuits

17 questions

1. Consider the circuit of an operational amplifier given here in which Zener diodes $Z_1$ and $Z_2$ are having reverse breakdown voltage = 7.4 V and forward voltage drop = 0.6 V. (i) Draw the output voltage waveform showing voltage value with time and calculate frequency of output waveform. (ii) Modify the circuit for duty cycle factor $D=0.25$ by replacing $R_1$ from combination of suitable resistances and diodes, so that output frequency is not changed.

[Figure: Op-amp astable circuit, supplies +12 V and −12 V. Inverting (−) input at node $V_1$; capacitor $C_1=0.1\mu F$ from $V_1$ to ground. Op-amp output through $R_2=1K$ to node $V_3$ (OUTPUT). Feedback resistor $R_1=100K$ from $V_3$ back to $V_1$. Potential divider from $V_3$ to ground: $R_3=39K$ from $V_3$ to node $V_2$ and $R_4=1K$ from $V_2$ to ground; $V_2$ is connected to the non-inverting (+) input. Two Zener diodes $Z_1$ and $Z_2$ in series back-to-back from $V_3$ to ground ($Z_1$ cathode at $V_3$, $Z_2$ cathode at ground, anodes joined)] [2025/20m/2b]

2. Explain the working of the given OPAMP circuit. Draw the output waveforms at points $A$ and $B$ showing the time and voltage. Given that, $V_{Z_1}=V_{Z_2}=3.3V$, $C_1=1\mu F$, the power supply voltage to OPAMPs is ±12 V and $R_1=R_2=R_3=R_4=R_5=R_6=2k\Omega$:

[Figure: Three op-amps $I_1$, $I_2$, $I_3$. $I_1$: inverting (−) input grounded; non-inverting (+) input at a node F. Output of $I_1$ through $R_3$ to node D. From D to ground: two Zener diodes $Z_1$ and $Z_2$ in series, back to back. $R_2$ from D back to node F. From D, $R_4$ to the inverting input of $I_2$; capacitor $C_1$ from the inverting input of $I_2$ to its output; non-inverting input of $I_2$ grounded; output of $I_2$ is point A. $R_1$ from output A back to node F. Node D is also connected to the non-inverting (+) input of $I_3$; output of $I_3$ is point B; $R_6$ is connected between the inverting (−) input of $I_3$ and a node joined to output B, and $R_5$ from that node to ground.]

Suggest to replace suitable resistances so that the output voltages at $A$ and $B$ are having swing of ±6 V and the output frequency is fixed to 500 Hz. [2024/20m/3b]

3. Determine the feedback fraction and the operating frequency for the oscillator circuit shown in Figure 6(c).

[Figure: Figure 6(c): Colpitts-type oscillator with an NPN transistor, emitter grounded. Collector connected to $V_{CC}$ through RFC = 100 μH. Base bias: $R_{B_1}$ from $V_{CC}$ to base, $R_{B_2}$ from base to ground. Collector node connected to: the top of inductor $L_1=1\mu H$; the top of capacitor $C_2=10pF$; and, through coupling capacitor $C_C=100pF$, to the output $v_o$. The lower end of $C_2$ and the upper end of $C_1=100pF$ join at a node connected to ground; the lower end of $C_1$ and the lower end of $L_1$ join and are connected by a wire back through a second coupling capacitor $C_C=100pF$ to the base] [2018/10m/6c]

4. Find the average voltage at the point $V_o$ in the circuit given in Fig. 4(c):

[Figure: Fig. 4(c): Op-amp supplied from +15 V and −15 V, output $V_o$. Source $v\left(t\right)=5sin\omega t$, $\omega =2*\pi *50$, with its lower terminal grounded; its upper terminal connects through a 1 kΩ resistor to the inverting (−) input. The non-inverting (+) input is connected to a node that goes to ground through a Zener diode (cathode at the node, anode at ground) and to the output $V_o$ through a 1 kΩ feedback resistor. Zener data: $V_Z=2.5$ V (Zener voltage), $V_{FZ}=0$ V (Forward voltage drop)] [2017/10m/4c]

5. (i) Draw the circuit diagram of Wien bridge oscillator using OP-AMP. (ii) Find the value of R to get a sustained oscillation of 1115 Hz. Assume that the value of the capacitor is $0.1\mu F$. [2017/10m/6c]

6. Figure shows a sinusoidal oscillator. By an appropriate analysis, determine the condition of oscillation and frequency of oscillation in terms of circuit elements assuming ideal op-amps.

[Figure: Three op-amp stages in cascade with an overall feedback loop. Stage 1: from the input node $R_o$ to the inverting (−) input and $C_1$ to the non-inverting (+) input; $R_1$ from the (+) input to ground; feedback resistor $R_o$ from the output to the (−) input. Stage 2 (fed from stage 1 output): identical with $R_o$ (input to −), $C_2$ (input to +), $R_2$ from (+) to ground and feedback $R_o$. Stage 3: inverting amplifier with input resistor $R_3$ from stage 2 output to the (−) input, feedback resistor $R_4$ from output to (−) input, (+) input grounded; its output is $V_o$, which is also fed back by a wire to the input node of stage 1] [2012/20m/3c]

7. Explain the operation of the given circuit by sketching relevant waveforms assuming that positive and negative saturation levels of output voltage of the op-amp comparator are $+V_{sa{t}_1}$ and $-V_{sa{t}_2}$ respectively and are not equal. Determine an expression for the frequency of the generated output voltage.

[Figure: Op-amp (supplies +V and −V′) astable circuit: resistor R from the output $V_o$ to the inverting (−) input; capacitor C from the (−) input to ground; resistor $R_b$ from the output to the non-inverting (+) input; resistor $R_a$ from the (+) input to ground] [2012/20m/4c]

8. Using an OP-AMP, several capacitors of 0.1 μF and number of resistances of your choice, design a phase-shift oscillator to oscillate at 100 Hz. [2011/20m/4a]

9. Using an opamp and RC network, explain the working of a Wien bridge oscillator. For a frequency of 1 kHz, design a Wien bridge oscillator. [2010/10m/7a(i)]

10. Derive the condition of oscillation and the expression for the frequency of oscillations for the circuit shown. (Use mesh analysis and Barkhausen’s criteria). Draw actual oscillator circuit with one operational amplifier and minimum number of RC elements.

[Figure: RC phase-shift network: three equal capacitors C in series along a horizontal line from the left node $V_0$ to the right terminal V; resistor R from the left node $V_0$, from the junction of the first and second capacitors and from the junction of the second and third capacitors to a common bottom line, which is grounded; an amplifier block A drawn above the network, with a wire rising from the left node $V_0$ and a wire rising from the right terminal V towards it (connections to the amplifier not completely drawn)] [2007/15m/4a(i)]

11. Explain with the help of neat diagram, the operation of a Schmitt trigger employing OP-AMP. [2007/10m/8a(i)]

12. Discuss the criteria for a circuit to oscillate. Explain the operation of a phase shift oscillator and derive an expression for the frequency of oscillation of an RC phase shift oscillator. [2003/20m/6a]

13. Obtain the conditions under which the circuit below produced oscillations.

[Figure: Op-amp Wien-bridge oscillator. The op-amp output (terminal of $v_o$, measured with respect to the bottom ground wire) is connected to a top wire. From the top wire: (1) resistor R in series with capacitor C down to node P; node P connected to the non-inverting (+) input; resistor R and capacitor C in parallel from node P to the bottom (ground) wire; (2) resistor $R_1$ from the top wire down to node Q; node Q connected to the inverting (−) input; resistor $R_2$ from node Q to the ground wire. $v_o$ is taken between the output and ground.]

What is the frequency of oscillations? [2002/20m/4a]

14. The simplified circuit of a radio oscillator is shown in Fig. above. Draw its equivalent circuit and obtain the condition of oscillation. Obtain the frequency of oscillation and the value of $h_{fe}$ required for the oscillation in the case of Hartley oscillator.

[Figure (printed above the text): Transistor oscillator (common emitter, emitter grounded). Impedance $Z_1$ between the top wire (connected to the collector) and the base; impedance $Z_3$ [?] between the base and the bottom (ground) wire; impedance $Z_2$ [?] between the top (collector) wire and the bottom (ground) wire on the right. Subscripts of the two lower/right boxes are blurred.] [2001/20m/6b]

15. Explain the operation of colpitts oscillator. A colpitts oscillator has a tank circuit as shown in the above figure. Calculate its frequency of oscillation. What should be the minimum gain of the amplifier for the oscillations to start?

[Figure: Colpitts tank circuit: two capacitors in series, 0.001 μF (upper) and 0.01 μF (lower), connected in parallel with a 12 μH inductor; the junction of the two capacitors is brought out through a capacitor to the (grounded) common terminal] [1999/20m/8b]

16. Draw the circuit diagram of an R-C phase shift oscillator using a transistor with CE configuration and derive an expression for its frequency of oscillation. Prove that $H_{fe}=23+29\frac{R}{R_L}+4\frac{R_L}{R_1}$ [1998/20m/7c]

17. The input $v_i\left(t\right)$ in the circuit of Fig. 5d is $v_i\left(t\right)=1.5sin2\pi \times {10}^{3}t$ volt with t in sec, Sketch $v_0\left(t\right)$ and label important points.

[Figure: Fig. 5d: Op-amp; source $v_i\left(t\right)$ connected between the upper input terminal of the op-amp and ground; the lower input terminal is connected to ground through a 1 kΩ resistor and to the output through a 3 kΩ resistor; output $v_o\left(t\right)$ taken with respect to ground (input polarity marks on the op-amp not legible; the arrangement is a regenerative comparator)] [1996/10m/5d(ii)]

4.8] Power supplies

3 questions

1. In the linear regulated power supply circuit shown here, calculate the output voltage adjustment range and maximum power dissipation in transistor $T_1$ in worst case:

[Figure: Input 15 V to 20 V DC between the top rail and the grounded bottom rail. 1 kΩ from the input rail to node Z; 12 V Zener diode (+ at top) from Z to ground. Across the Zener (from Z to ground): 1 kΩ, a 10 kΩ potentiometer and 1 kΩ in series; the potentiometer wiper goes to the non-inverting (+) input of op-amp $I_1$. Op-amp $I_1$ is supplied from the input rail and ground. Output of $I_1$ through 470 Ω to the base of $T_1$; collector of $T_1$ to the input rail; emitter of $T_1$ through 0.7 Ω to the output terminal. Transistor $T_2$: base at the emitter of $T_1$ (top of the 0.7 Ω), emitter at the output end of the 0.7 Ω, collector at the base of $T_1$. The inverting (−) input of $I_1$ is connected to the output terminal. Output taken between this terminal and the grounded rail.]

($T_1$ and $T_2$ are Si transistors) [2024/10m/4b(ii)]

2. Design a voltage regulator using 7805 IC to get a voltage output of 8 V. [2013/10m/4b]

3. A simple voltage regulator circuit is shown in Fig 4(c). The zener voltage is given by $V_z=(10+0.20i_z)$ volts where $i_z$ is in mA. For a given transistor, assume $\beta =100$ and $V_{BE}=0.3$ V (constant). Determine % load regulation if maximum load current of 500 mA is switched off.

[Figure: fig.4 (c): Series (emitter-follower) regulator: 20 V d.c. input between the + and − input terminals; NPN transistor ($\beta =100$, $V_{BE}=0.3$ V) with collector to the + input line and emitter to the load (load current 500 mA); 500 Ω resistor from the + input line to the base; zener diode ($V_z$) from the base to the − line (cathode at the base); the load block connected between the emitter and the − line] [1998/20m/4c]

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